Flash Memory Cache Block Allocation for Write Efficiency
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Solution Overview
Problem
Existing FLASH memory data storage devices face inefficiencies in operation due to the need for frequent valid data collection and erase operations, particularly in block mapping modes, which burden performance, and in page mapping modes, where large resource-consuming mapping tables are required for lookup.
Innovation Solution
A data storage device with a FLASH memory and a controller that employs shared and dedicated cache blocks to manage data blocks, where hot data is cached in dedicated blocks and non-hot data is cached in shared blocks, reducing the frequency of valid data collection and erase operations, and utilizing efficient caching and mapping tables to optimize storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If block mapping mode is used to allocate physical blocks to consecutive logical addresses, then data storage organization is simplified, but frequent valid data collection operations are required which burden operation efficiency
Solution Approach 1:
The patent segments the cache into multiple cache lines, where each cache line can be independently managed. This allows the system to perform valid data collection on a per-cache-line basis rather than requiring full block erasure, thereby reducing the frequency and impact of garbage collection operations while maintaining simplified data organization.
Solution Approach 2:
The patent implements dynamic cache line invalidation and valid data collection mechanisms. Cache lines are dynamically marked as valid or invalid based on write operations, and the system performs incremental valid data collection only on affected cache lines rather than entire blocks, improving operation efficiency while preserving organizational simplicity.
2Adaptability or versatility
If page mapping mode is used to allow non-sequential writes, then write flexibility is improved, but large mapping tables are required which consume significant resources
Solution Approach 1:
The patent segments the mapping structure into smaller cache line-level entries rather than requiring comprehensive block-level or page-level mapping tables. Each cache line maintains its own validity state and mapping information, reducing the overall memory footprint of the mapping structure while preserving write flexibility.
Solution Approach 2:
The patent introduces cache lines as an intermediary layer between physical blocks and logical addresses. This intermediary structure allows the system to maintain write flexibility without requiring large mapping tables, as the cache line validity bits and partial mapping information serve as a compact intermediary representation.
3Ease of operation
If entire physical blocks are erased to release space, then space reuse is enabled, but the erase operation time is considerable which reduces performance
Solution Approach 1:
The patent segments the erasure operation into cache line-level invalidation instead of block-level erasure. When space needs to be released, only the specific cache lines containing invalid data are targeted for collection and erasure, rather than erasing entire physical blocks. This segmentation dramatically reduces erase operation time while maintaining space reuse capability.
Solution Approach 2:
The patent performs preliminary valid data collection and invalidation at the cache line level before erasure operations. By proactively managing cache line validity states and collecting valid data incrementally, the system prepares for erasure in advance, reducing the actual erasure time required when space needs to be released.
Data Source
AI summary
A data storage device with a FLASH memory and an operating method for the data storage device are disclosed. According to the disclosure, the space of the FLASH memory is allocated to include groups of data blocks, a plurality of shared cache blocks (SCBs) and a plurality of dedicated cache blocks (DCBs). Each SCB is shared by one group of data blocks, for the write data storage when any data block of the group of data blocks is exhausted. The DCBs are allocated for the hot data storage. Each DCB corresponds to one hot logical block.