Flash Cache Tag Prioritization for External Memory Access Speed
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Solution Overview
Problem
Conventional methods for handling flash code in processor chips with external flash devices are inadequate for efficient execution due to low access speed, particularly for ROM patch codes and new application codes, as they lack effective mapping and prioritization mechanisms.
Innovation Solution
A cache system that includes a processor chip with a comparing device to match processing unit addresses with tag memory information, a mapping device to temporarily store and prioritize external memory data, and a masking mechanism to vary block sizes, enabling efficient handling of ROM patch codes and application codes by prioritizing and remapping cache lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If flash code is transferred to internal RAM before execution, then execution speed is improved, but memory access complexity and device complexity increase
Solution Approach 1:
The tag memory is divided into multiple tag sets, with each tag set containing multiple tag entries. This segmentation allows parallel comparison operations and enables the system to handle multiple flash code segments simultaneously, reducing the complexity of managing large blocks of memory while maintaining high execution speed.
Solution Approach 2:
A flash cache block is introduced as an intermediary component between the external flash device and the processor core. This cache block includes tag memory and data memory, acting as a buffer that pre-loads and manages flash code, thereby reducing direct access complexity to the flash device while maintaining fast execution speeds.
2Device complexity
If conventional mapping methods are used for flash code locations, then device simplicity is maintained, but adaptability for handling patch codes and new application codes deteriorates
Solution Approach 1:
The tag memory structure is designed to be dynamically configurable, allowing the flash cache block to adapt to different code types (patch codes, new application codes) and different mapping scenarios. The tag sets and tag entries can be selectively activated and configured based on the specific code being executed, providing versatility without requiring complete redesign for each code type.
Solution Approach 2:
The system allows changing of mapping parameters such as tag set selection, tag entry configuration, and data memory allocation based on the type of flash code being executed. By dynamically adjusting these parameters, the system can efficiently handle different code formats and mapping requirements using the same underlying hardware structure.
3Quantity of substance
If external flash device is used for code storage, then storage capacity is improved, but access speed deteriorates
Solution Approach 1:
The flash cache block performs preliminary actions by pre-loading flash code from the external flash device into the internal data memory before execution is needed. The tag memory is pre-configured with tag sets and tag entries that map flash code locations to internal memory locations, so that when code execution is required, the mapping is already established and data can be quickly retrieved without real-time translation delays.
Data Source
AI summary
A cache system includes a processor chip to receive a processing unit address. The cache system also includes a comparator to compare the processing unit address to an address information stored in an allocated tag subset of a tag memory of the processor chip to determine whether the processing unit address matches the address information. The cache system further includes a mapping device to map the portion of the address information to an external memory data, temporarily stored in an allocated data memory subset and a corresponding data memory set of a data memory in the processor. Furthermore, the cache system includes a stacking loop to prioritize the allocated tag subset and a corresponding tag set when the processing unit address matches the address information.