Interdigitated Flash Capacitor Layout for High-Voltage Charge Pumps
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Solution Overview
Problem
Modern flash memory technologies require high voltages for erase and program operations, which are costly to achieve due to the use of traditional capacitors like PIP, MIM, or MoM in integrated charge pump circuits, involving extra masks and process steps.
Innovation Solution
An inter-digitated capacitor is formed alongside split-gate flash memory cells, providing high capacitance per unit area, comprising a well region with trenches, lower electrodes separated by a charge trapping dielectric layer, and upper electrodes laterally separated from lower electrodes by another dielectric layer, allowing for efficient high-voltage generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If traditional capacitors (PIP, MIM, or MoM) are used in integrated charge pump circuits, then high voltage generation is achieved, but device complexity and manufacturing cost increase due to extra masks and process steps
Solution Approach 1:
The patent combines the capacitor formation process with the existing flash memory cell fabrication process. The inter-digitated capacitor electrodes are formed using the same trench structures and dielectric layers that are already present in the split-gate flash memory cell, eliminating the need for separate capacitor fabrication steps, masks, and processes.
Solution Approach 2:
The patent creates a multi-functional structure where the same trench structures serve dual purposes: forming both the flash memory cell components (control gate, charge trap layer) and the capacitor electrodes. The dielectric layers and electrode structures are designed to function as both memory cell elements and capacitor elements, reducing overall device complexity.
2Stress or pressure
If traditional capacitors are used in integrated charge pump circuits, then high voltage generation is achieved, but manufacturing cost increases due to extra masks and process steps
Solution Approach 1:
The patent merges the capacitor formation with the flash memory cell fabrication process, so that both structures are created simultaneously using the same process steps, masks, and materials. This integration eliminates the need for additional manufacturing steps and reduces overall production cost.
Solution Approach 2:
The existing flash memory cell structures (trenches, dielectric layers, electrodes) automatically serve as the capacitor structures as well. The same physical features that form the memory cell also form the capacitor, so no additional manufacturing resources are required for capacitor fabrication.
3Quantity of substance
If inter-digitated capacitor is formed alongside split-gate flash memory cells, then capacitance per unit area increases, but device structure becomes more complex
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional inter-digitated structures with vertical trenches. By utilizing the vertical dimension and creating interleaved electrode patterns, the capacitor achieves significantly higher capacitance per unit area while the complexity is managed through the natural vertical stacking of the split-gate flash memory cell structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The inter-digitated capacitor reduces the complexity and cost of high-voltage generation, enabling effective erase and program operations while maintaining low power consumption and immunity to short channel effects.
Implementation Method 1
An inter-digitated capacitor is formed alongside split-gate flash memory cells, providing high capacitance per unit area
Implementation Method 2
A charge trapping dielectric layer is arranged between the substrate and the plurality of lower electrodes and between the plurality of upper electrodes and the plurality of lower electrodes
Data Source
AI summary
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having sidewalls that define a recess within an upper surface of the semiconductor substrate. A plurality of upper electrode segments are arranged over the semiconductor substrate and are vertically separated from the upper surface of the semiconductor substrate by a first dielectric layer. A lower electrode segment is arranged directly between the sidewalls of the semiconductor substrate and directly between adjacent ones of the plurality of upper electrode segments. A second dielectric layer is arranged directly between the sidewalls of the semiconductor substrate and the lower electrode segment and also directly between the plurality of upper electrode segments and the lower electrode segment.