Flash Cell Check Engine for Ultra-Fast Pattern Matching

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Solution Overview

Problem

Conventional memory-based systems for pattern checking introduce latency and vulnerability to interception by requiring the read and conveyance of reference patterns, which slows down the matching process and compromises security.

Innovation Solution

An ultra-fast check engine based on flash cells that performs pattern matching in situ, eliminating the need to read and convey reference patterns, allowing for rapid comparison within the check engine, thereby reducing latency and enhancing security.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If reference pattern is read from memory array and conveyed to another part of the system, then pattern matching can be performed, but latency is introduced and security is compromised

Engineering Contradiction:
ImprovesecurityVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the memory array and comparison logic into a single integrated structure where reference patterns are stored directly in the memory array and compared in-place. This eliminates the need to read and convey reference patterns to a separate crypto-processor, thereby reducing latency and maintaining security by keeping sensitive data within the memory array throughout the comparison process.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If reference pattern is read from memory array, then pattern matching can be performed, but matching speed is reduced

Engineering Contradiction:
Improvematching speedVSAvoidread time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by pre-positioning the reference pattern directly in the memory array cells where it can be accessed and compared simultaneously with target patterns. This eliminates the sequential read operation that would otherwise be required, enabling parallel comparison operations to proceed immediately without waiting for data retrieval, thus significantly improving matching speed.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If reference pattern is conveyed through data bus, then pattern matching can be performed, but vulnerability to interception is introduced

Engineering Contradiction:
ImprovesecurityVSAvoidsystem operation
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent extracts the vulnerable data transmission step from the pattern matching process by eliminating the need to convey reference patterns through data buses. Instead, the comparison is performed in-place within the memory array, removing the intermediate transmission step that creates security vulnerabilities while maintaining full pattern matching functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9218879B2Apparatus, system, and method for matching patterns with an ultra fast check engine based on flash cells
Publication Date: 2015.12.22 ALLEGRO MICROSYSTEMS LLC
  • US9218879B2 patent drawing
  • US9218879B2 patent drawing
  • US9218879B2 patent drawing

AI summary

A check engine includes comparators, where each comparator has flash cells. Each comparator is configured to store at least one reference bit included in a set of reference bits defining a first pattern. Each comparator also includes an input for presenting at least one target bit included in a set of target bits defining a second pattern. Each comparator is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit. The check engine is configured such that the outputs of the comparators are combined to produce a combined output that is compared to a reference signal to determine whether there is a match between the first pattern and the second pattern.