Multi-Bit Flash Cell Encoding for Even Error Distribution
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Solution Overview
Problem
Multi-bit flash memory cells face challenges in efficiently storing and reading data due to the need for multiple comparisons to identify the correct threshold voltage range, leading to suboptimal bit orderings that do not evenly distribute error probabilities, resulting in inefficient data storage and retrieval.
Innovation Solution
A method of programming each cell with up to M bits according to a valid physical bit ordering and a logically different ordering that distributes error probabilities more evenly, using a translation mechanism to map logical to physical bit orderings, ensuring valid and error-rate-optimal bit allocations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple comparisons are used to identify the correct threshold voltage range in multi-bit flash cells, then reading accuracy is improved, but the number of operations and time required increases
Solution Approach 1:
The patent applies preliminary action by pre-establishing a mapping between logical bit orderings and physical bit orderings that are optimized for error distribution. This mapping is determined in advance during cell programming, allowing the system to skip unnecessary comparisons during read operations. The logical-to-physical ordering transformation is performed once during programming, enabling faster reads without sacrificing accuracy.
Solution Approach 2:
The patent segments the bit storage into logical bits and physical bits with different orderings. By dividing the bit sequence into logical ordering (optimized for error distribution) and physical ordering (optimized for reading efficiency), the system can independently optimize each aspect. This segmentation allows the physical ordering to minimize comparisons while the logical ordering ensures error resilience.
2Device complexity
If a simple physical bit ordering is used for programming multi-bit flash cells, then programming complexity is reduced, but error probability distribution becomes uneven
Solution Approach 1:
The patent introduces an additional dimension by creating a mapping between two different orderings (logical and physical). Instead of using a single ordering, the system transforms data from logical ordering to physical ordering during programming and back during reading. This dimensional transformation allows the system to achieve both simple programming and even error distribution by operating in the logical domain while storing in the physical domain.
Solution Approach 2:
The logical bit ordering acts as an intermediary between the data to be stored and the physical storage medium. The logical ordering provides an even error distribution, while the physical ordering optimizes for reading efficiency. The mapping between these two orderings serves as the intermediary mechanism that reconciles the conflicting requirements of programming simplicity and error resilience.
3Reliability
If nonserial bit ordering is implemented to optimize error distribution, then error rate is reduced, but the complexity of bit mapping increases
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing the mapping between logical and physical bit orderings. This mapping is established once during cell programming and then reused for all subsequent read operations. The complex nonserial ordering transformation is performed in advance, allowing the read operations to use simpler reverse lookups, thereby reducing the overall system complexity despite the sophisticated ordering scheme.
Data Source
AI summary
Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2M−1 transitions. Preferably, the logical bit ordering is evenly distributed. The translation between the bit orderings is done by software or hardware.