Flash Memory Cell Erase Condition Using High Voltage State
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Solution Overview
Problem
Conventional flash memory devices lack the ability to perform single logical cell erasure and support byte alterability, as they typically require sector or block-level erasure, which is inefficient and limits programming flexibility.
Innovation Solution
The implementation of a single program and erase entity, comprising two adjacent physical memory cells, allows for logical cell mapping and the use of a high voltage state as an erased state, enabling single logical cell erasure and programming on a byte or variable length basis by changing the voltage state between low and high voltage states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sector or block-level erasure is used in conventional flash devices, then erase operation can be performed, but erase time is long and programming flexibility is limited
Solution Approach 1:
The patent divides the memory into multiple independently erasable blocks, where each block can be erased individually rather than requiring sector or block-level erasure. This segmentation enables single logical cell erasure while maintaining the ability to perform erasure operations at different granularities, thus improving both erase speed and programming flexibility.
2Reliability
If conventional low voltage state is used as erased state, then binary value representation is maintained, but device wear increases due to over-erase operations
Solution Approach 1:
The patent inverts the conventional voltage state assignment by using high voltage state as the erased state and low voltage state as the programmed state. This inversion eliminates the need for over-erase operations, reduces device wear, and enables more efficient erase operations since cells can be directly erased to the high voltage state without requiring pre-programming.
3Adaptability or versatility
If single logical cell erasure is enabled, then programming flexibility is improved, but device complexity increases due to additional circuitry
Solution Approach 1:
The patent designs the memory architecture where blocks can serve multiple functions: they can be individually erased for fine-grained programming flexibility, or multiple blocks can be combined to form larger erasable units when needed. This multi-functionality allows the system to adapt to different programming requirements without requiring entirely separate circuitry for each operation type.
Data Source
AI summary
Aspects describe a system and method for using a high voltage state as an erase condition in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a single logical cell, thereby creating a single program and erase entity. Logical cell erase, program, and/or read can be accomplished by using two channel regions in union. This combination can allow for single logical cell erasure in a flash device and the use of a high voltage state as an erased state. A default erased state can be a high voltage state. As a result, program operations can be performed by changing a voltage state of the single program and erase entity to a low voltage state, and erase operations can be performed by changing a voltage state of the single program and erase entity to a high voltage state.