Flash Memory Cell Wear-Leveling via Binary Data Counting

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Solution Overview

Problem

Existing wear-leveling algorithms for flash memory devices operate at the block level, leading to uneven wear across flash blocks due to varying numbers of '0's and '1's being written, causing some blocks to wear out significantly faster than others, despite equal erase-write cycles.

Innovation Solution

A cell-based wear-leveling method that counts the number of '0's and '1's in incoming data chunks and distributes writing across cells to maintain even wear, using wear-leveling information to identify the least and most worn-out cells for optimal data placement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If block-level wear-leveling is used to distribute erase-write operations evenly across flash blocks, then the number of erase cycles per block is balanced, but the actual wear on cells remains uneven due to varying numbers of '0's written to different blocks

Engineering Contradiction:
ImproveenduranceVSAvoidwear distribution uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The invention segments the wear-leveling granularity from block level to cell level. Instead of treating entire flash blocks as the unit for wear distribution, the system tracks and distributes wear at the individual cell level within blocks. This is achieved by maintaining wear counters for each cell and selectively erasing only the necessary cells rather than entire blocks, thereby achieving more precise wear control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention applies local quality by treating different cells within the same block differently based on their individual wear states. The system identifies specific cells that have accumulated excessive wear (high '0' count) and targets them for erasure, rather than uniformly erasing entire blocks. This localized approach ensures that wear is distributed more evenly across all cells regardless of their block assignments.

Inventive Principle:
Principle #3Local quality

2Productivity

If flash blocks are erased and rewritten with equal frequency, then block-level wear appears balanced, but cells within blocks experience different wear due to random data patterns with varying numbers of '0's

Engineering Contradiction:
Improveerase-write cycle efficiencyVSAvoidcell lifespan
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The invention performs preliminary action by proactively tracking the wear state of each cell through wear counters that monitor the number of '0's written to each cell. Before a cell reaches its endurance limit, the system identifies it as needing erasure and schedules it accordingly. This preventive approach allows the system to redistribute wear before critical failure occurs, rather than reacting after damage has accumulated.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms by continuously monitoring wear counters for each cell and using this information to make dynamic decisions about which cells to erase and rewrite. The wear counter data feeds back into the wear-leveling algorithm, which adjusts erasure and write operations in real-time to maintain even wear distribution across all cells, thereby extending overall device lifespan.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9170933B2Wear-level of cells/pages/sub-pages/blocks of a memory
Publication Date: 2015.10.27 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9170933B2 patent drawing
  • US9170933B2 patent drawing
  • US9170933B2 patent drawing

AI summary

A method for wear-leveling cells, pages, sub-pages or blocks of a memory such as a flash memory includes receiving (S10) a chunk of data to be written on the cell, page, sub-page or block of the memory; counting (S40), in the received chunk of data, a number of times a given type of binary data ‘0’ or ‘1’ is to be written; and distributing (S50) the writing of the received chunk of data among cells, pages, sub-pages or blocks of the memory such as to wear-level the memory with respect to the number of the given type of binary data ‘0’ or ‘1’ counted in the chunk of data to be written.