Flash Array Charge Pump Architecture for Independent Sub-Array Voltage Control
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Solution Overview
Problem
Current flash memory technologies face challenges in managing voltage levels for efficient write and erase operations in System-on-Chip (SoC) devices, particularly at lithography nodes below 28 nm, where the size of embedded non-volatile memory becomes difficult to manage and requires enhanced voltage boosting capabilities.
Innovation Solution
The introduction of an intelligent charge pump architecture that includes a register block and logic circuit portion, integrated with a JTAG protocol, allows for the generation of required voltage levels within the flash memory array without external support, enabling concurrent operations across multiple sub-arrays and reducing latency through direct memory access configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external voltage support is used for flash memory operations, then voltage boosting capability is sufficient, but device complexity and external component requirements increase
Solution Approach 1:
The patent extracts the voltage boosting function from external support devices and integrates it into the flash memory array itself through embedded charge pump circuits. This allows the system to maintain sufficient voltage boosting capability while eliminating external component requirements, directly resolving the technical contradiction between reliability and device complexity.
Solution Approach 2:
The flash memory array becomes self-sufficient by incorporating intelligent charge pump architecture that generates required voltage levels internally without external support. The system serves its own voltage boosting needs through integrated circuits, eliminating dependency on external components while maintaining operational reliability.
2Productivity
If voltage levels are increased for write and erase operations, then operation efficiency improves, but power consumption increases
Solution Approach 1:
The patent implements dynamic voltage control through intelligent charge pump architecture that adjusts voltage levels based on operational requirements. During write and erase operations, voltage is boosted to required levels for efficient operation, while during read operations or idle states, voltage is reduced to minimize power consumption, thus resolving the contradiction between operation efficiency and power consumption.
Solution Approach 2:
The system dynamically changes voltage parameters according to operational mode. The intelligent charge pump architecture modifies voltage levels adaptively - increasing voltage during write/erase operations to improve efficiency, and reducing voltage during other operations to decrease power consumption, thereby balancing productivity and energy usage.
3Productivity
If concurrent operations across multiple sub-arrays are enabled, then throughput increases, but voltage control complexity increases
Solution Approach 1:
The patent divides the flash memory array into multiple sub-arrays, each with its own intelligent charge pump architecture. This segmentation allows concurrent operations across different sub-arrays to increase throughput while distributing voltage control complexity across multiple independent units, making the overall system more manageable and scalable.
Solution Approach 2:
The intelligent charge pump architecture is designed as a universal, multi-functional unit that can serve multiple sub-arrays. Each charge pump unit can independently control voltage for read, write, and erase operations across its assigned sub-arrays, enabling concurrent operations while maintaining standardized control mechanisms that prevent excessive complexity.
4Quantity of substance
If lithography node is scaled below 28 nm, then device density increases, but voltage management difficulty increases
Solution Approach 1:
The patent implements preliminary voltage generation and management through embedded charge pump circuits that are integrated into the flash memory array before data operations. This preliminary action ensures that required voltage levels are already available and properly managed at the point of use, eliminating the need for complex external voltage management infrastructure even as device density increases at scaled lithography nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the scalability and performance of flash memory arrays by providing independent voltage control for read, write, and erase operations, improving access time and throughput while maintaining reliability and flexibility in voltage generation.
Implementation Method 1
The operating mechanism is made using a non-overlapping two phases clock. The purpose is to store charge in a capacitance, using one phase, and transfer that charge to another capacitance, using another phase. A proper modulation of the phases allows the charge pump to store the charge in a capacitance and transfer it to the other one, increasing the equivalent value Vs a reference.
Data Source
AI summary
The present disclosure relates to a non-volatile memory device and to a method for generating overvoltage values in such a memory device structured in a plurality of sub-arrays and including at least a decoding and sensing circuitry associated with each sub-array, a charge pump architecture for each sub-array including pump stages for increasing the value of an input voltage and obtaining an overvoltage output value, a control and JTAG interface in the memory device, and at least a registers block coupled to the charge pump architecture and driven by a logic circuit portion for receiving at least an activation signal selecting a specific charge pump architecture associated with a memory sub-array of the plurality of sub-arrays.