Flash Chip Read Write Control Circuit for AMOLED Data Integrity
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Solution Overview
Problem
Conventional flat panel display circuits do not allow for write operations to flash chips after the product leaves the factory, leading to data loss during abnormal events like power outages, as write operations cannot be completed before erasure, resulting in abnormal display content after re-energization.
Innovation Solution
A read and write control circuit for flash chips that includes a timing control circuit and non-volatile memory to manage flags for each block, copying data to a backup area, setting flags for write states, and determining data sources post-re-energization to prevent data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If write operations are enabled to flash chip during product use for AMOLED electrical compensation, then the functionality and adaptability are improved, but the risk of data loss during abnormal events increases
Solution Approach 1:
The patent applies preliminary action by copying data to a backup memory area before performing write operations to the flash chip. This ensures that if an abnormal event occurs during writing, the original data can be restored from the backup, thus enabling write operations for electrical compensation while protecting against data loss.
Solution Approach 2:
The patent implements beforehand cushioning by setting a flag to indicate abnormal write state and preparing a backup memory area in advance. This cushioning mechanism protects the system from data loss when abnormal events occur during write operations, allowing the flash chip to be written during use while maintaining data integrity.
2Reliability
If data is copied to backup memory area before write operation, then data loss is prevented, but the writing time and processing duration increase
Solution Approach 1:
The patent applies partial action by only copying data to backup memory when a write operation is initiated, rather than continuously copying. The flag mechanism further optimizes this by only triggering backup operations when abnormal write states are detected, thus preventing data loss while minimizing the additional time required.
3Reliability
If flag management mechanism is implemented to track write states, then data integrity is improved, but the device complexity increases
Solution Approach 1:
The patent applies self-service by using a simple flag bit that automatically indicates the write state without requiring complex control logic. The timing control circuit automatically checks the flag and manages the backup process, reducing the need for additional complex control mechanisms while maintaining reliable write state tracking.
Data Source
AI summary
A read and write control circuit for a flash chip is disclosed which includes a timing control circuit for generating a read and write timing signal for the flash chip, and a first non-volatile memory for storing a plurality of flags corresponding to a plurality of blocks in the flash chip, each of the flags indicating whether a respective one of the blocks that corresponds thereto has been written to normally. Also disclosed is a read and write control method of a flash chip, as well as an AMOLED application circuit having the read and write control circuit for use in an electrical compensation mechanism.