Flash-CMOS IC Fabrication Across Separate Voltage Domains
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Solution Overview
Problem
The integration of non-volatile Flash memory with CMOS logic circuitry in a single semiconductor die is challenging due to the need to satisfy different technical specifications and operational voltages, leading to potential performance mismatches and increased manufacturing costs.
Innovation Solution
A modularized process flow is adopted to fabricate Flash memory and CMOS logic circuitry separately on a single semiconductor die, where Flash memory cells and high-voltage devices are processed first, followed by the formation of CMOS logic circuitry in a different voltage domain, allowing for decoupled processing and reduced transistor mismatch issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Flash memory and CMOS logic circuitry are integrated on a single semiconductor die, then device functionality and integration density are improved, but manufacturing complexity and transistor mismatch increase
Solution Approach 1:
The patent divides the semiconductor die into multiple regions with different gate oxide layer configurations. Specifically, it creates a first region with a first gate oxide layer for Flash memory cells and a second region with a second gate oxide layer for CMOS logic circuitry. This segmentation allows each region to be optimized independently for its specific function while being fabricated on the same die, thereby improving device functionality without excessively increasing manufacturing complexity.
Solution Approach 2:
The patent applies local quality by providing different gate oxide layer characteristics in different regions of the die. The first gate oxide layer in the Flash memory region has specific thickness and material properties optimized for non-volatile memory operation, while the second gate oxide layer in the CMOS logic region has different properties optimized for logic circuit operation. This localized optimization enables both Flash memory and CMOS logic to perform at their best on the same die.
2Reliability
If different voltage levels are used for Flash memory and CMOS logic circuitry, then operational performance is improved, but transistor mismatch and manufacturing difficulty increase
Solution Approach 1:
The patent implements local quality by creating region-specific gate oxide layers with different thicknesses and material compositions tailored to the voltage requirements of each circuit type. The first gate oxide layer is designed for the voltage levels required by Flash memory cells, while the second gate oxide layer is designed for the voltage levels required by CMOS logic circuitry. This approach allows optimal operational performance at different voltage levels while minimizing transistor mismatch through localized optimization rather than compromise designs.
Solution Approach 2:
The patent segments the transistor population into two groups based on their voltage requirements: Flash memory transistors in the first region and CMOS logic transistors in the second region. Each group receives a gate oxide layer specifically engineered for its voltage operating conditions. This segmentation prevents the transistor mismatch that would occur if a single gate oxide design had to serve both voltage domains.
3Adaptability or versatility
If separate processing steps are used for Flash memory and CMOS logic, then manufacturing flexibility is improved, but process complexity and fabrication time increase
Solution Approach 1:
The patent segments the fabrication process into region-specific processing steps that can be independently optimized and controlled. Different gate oxide layers are formed in different regions using tailored processing parameters, allowing the manufacturing process to be flexible in adapting to different product requirements while maintaining efficiency through parallel processing capabilities and reduced rework.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient fabrication of integrated circuits with both Flash memory and CMOS logic circuitry, reducing manufacturing defects, improving yield, and maintaining electrical performance across different voltage domains.
Implementation Method 1
a first transistor is formed in the first region and operable at a first voltage level, the first transistor including a gate formed over a first gate oxide layer exclusive of nitridation, and one or more sets of second transistors are formed in the second region, each set operable at a corresponding second voltage level different than the first voltage level and including a corresponding second gate oxide layer having nitridation
Data Source
AI summary
An integrated circuit (IC) including Flash memory and CMOS logic circuitry and a method of fabrication thereof is disclosed. The IC comprises a substrate including a first region and a second region, where a Flash memory cell gate stack is formed in the first region, a first transistor is formed in the first region and operable at a first voltage level, the first transistor including a gate formed over a first gate oxide layer exclusive of nitridation, and one or more sets of second transistors are formed in the second region, each set operable at a corresponding second voltage level different than the first voltage level and including a corresponding second gate oxide layer having nitridation.