Flash Memory Column Programming to Reduce Charge State Overlap

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Solution Overview

Problem

Conventional flash memory programming sequences result in undesirable charge distribution disturbances due to parasitic transistors, leading to overlapping charge states that hinder accurate data storage and retrieval, particularly in multi-level cell technologies.

Innovation Solution

Implementing a top-down programming approach and a corrective read algorithm to mitigate the disturb effect by adjusting read voltages based on the charge state of adjacent cells, thereby maintaining precise charge distributions and improving programming efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional bottom-up programming sequence is used, then programming process is simple, but charge distribution overlap occurs due to parasitic transistor effects

Engineering Contradiction:

Improveprogramming process simplicityVSAvoidcharge distribution accuracy

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent inverts the conventional bottom-up programming sequence to a top-down programming sequence. By programming cell stacks from the top (first cell stack) downward to subsequent cell stacks, the patent eliminates the charge distribution overlap caused by parasitic transistor effects that occur in the bottom-up approach. This inversion resolves the technical contradiction by maintaining programming process simplicity while achieving accurate charge distribution.

Inventive Principle:

Principle #13The other way round (Inversion)

2Manufacturing precision

If top-down programming approach is used, then charge distribution accuracy is improved, but programming process complexity increases

Engineering Contradiction:

Improvecharge distribution accuracyVSAvoidprogramming process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the programming process into distinct phases corresponding to different cell stacks, with the first cell stack programmed in a top-down manner within its page, followed by subsequent cell stacks. This segmentation allows the complex top-down programming approach to be applied selectively and systematically, managing the complexity while achieving accurate charge distribution for multi-level cell storage.

Inventive Principle:

Principle #1Segmentation

3Productivity

If conventional programming sequence is used, then programming speed is maintained, but read accuracy deteriorates due to charge state overlap

Engineering Contradiction:

Improveprogramming speedVSAvoidread accuracy

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

By inverting the programming sequence to top-down, the patent prevents charge distribution overlap that would otherwise require additional verification iterations and corrective reads. This maintains programming speed while significantly improving read accuracy, as the inverted sequence inherently produces well-separated charge states that are easier to distinguish during read operations.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS20250364059A1Flash memory having improved performance as a consequence of program direction along a flash storage cell column

Publication Date: 2025.11.27 INTEL NDTM US LLC

AI summary

A method is described. The method includes programming a column of flash storage cells in a direction along the column in which a parasitic transistor that resides between a cell being programmed and an immediately next cell to be programmed has lower resistivity as compared to a corresponding parasitic transistor that exists if the programming were to be performed in an opposite direction along the column.