Flash Controller Logical Address Group Table Garbage Collection
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Solution Overview
Problem
Existing flash module management systems require significant storage space and reduce processing efficiency due to the large amount of data needed for address information, making it difficult to correctly determine valid and invalid pages during garbage collection operations.
Innovation Solution
A method that uses a logical address group table to efficiently determine valid and invalid pages by referencing a physical to logical address mapping table, reducing the data amount required for address information storage and optimizing garbage collection operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-storing of address information is performed for garbage collection operations, then valid pages and invalid pages can be correctly determined, but the data amount of address information increases, reducing storage space and processing efficiency
Solution Approach 1:
The patent segments the address space into multiple blocks, where each block has its own indicator bit in the logical address group table. This allows the system to track address information at a coarser granularity level rather than storing detailed mappings for every address, significantly reducing the total data amount while maintaining the ability to correctly identify valid and invalid pages within each block
Solution Approach 2:
The patent introduces a logical address group table as an intermediary data structure between the flash module and the garbage collection process. This table uses compact indicator bits to represent the state of address groups, serving as a mediator that enables efficient garbage collection operations without requiring large amounts of detailed address information to be stored
2Reliability
If pre-storing of address information is performed for garbage collection operations, then valid pages and invalid pages can be correctly determined, but processing efficiency of the flash controller is reduced
Solution Approach 1:
By segmenting the address space into blocks with indicator bits, the patent enables the flash controller to quickly scan and identify candidate blocks for garbage collection without processing large amounts of detailed address information. This segmentation approach significantly improves processing efficiency while maintaining accurate identification of valid and invalid pages
Solution Approach 2:
The patent uses indicator bits that provide partial information about address group states rather than complete address mappings. This partial information is sufficient for the garbage collection process to identify candidate blocks efficiently, and only detailed L2P mappings are retrieved when needed, improving overall processing efficiency
Data Source
AI summary
The present invention provides a method for accessing a flash module, wherein the method includes: creating a logical address group table corresponding to a block of the flash module, wherein the logical address group table records states of a plurality of logical address groups, and the state of each logical address group represents if data written into the block has any logical address within the logical address group; when the block is under a garbage collection operation, referring to the logical address group table to read at least one logical address to physical address (L2P) mapping table; and determining valid pages and invalid pages within the block according to the L2P table, for performing the garbage collection operation.