Flash Controller Arbitration Circuit Peak Current Reduction
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Solution Overview
Problem
High-performance flash memory storage devices face challenges in reducing peak power consumption and package size due to increased number of flash control circuits, leading to high peak current when executing commands simultaneously.
Innovation Solution
A non-volatile memory storage device with a controller comprising multiple control circuits and an arbitration circuit that generates and acknowledges chip-enable (CE) requests, and an optional command interleaving circuit to coordinate the timing of these requests, ensuring all requests are acknowledged before updating CE signals and interleaving command execution to avoid peak current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of flash control circuits is increased to increase performance, then the data bus width and memory access capability are improved, but the peak current consumption increases dramatically
Solution Approach 1:
The patent applies preliminary action by having control circuits issue CE update requests in advance before actually updating CE signals. The arbitration circuit collects these requests and determines acknowledgment timing proactively, ensuring that CE signals are updated only when all requests are acknowledged. This prevents simultaneous command execution and reduces peak current while maintaining high memory access capability through coordinated control.
2Speed
If multiple control circuits operate independently to improve performance, then the data processing speed is improved, but the package size increases due to more CE pads
Solution Approach 1:
The patent merges the CE signal generation function from multiple independent control circuits into a single arbitration circuit. Instead of each control circuit having its own CE pad, the arbitration circuit consolidates CE signal output, reducing the number of CE pads required. Multiple control circuits can still operate in parallel with 16-bit data buses, maintaining high data processing speed while reducing package size through the merged CE control architecture.
3Productivity
If flash commands are executed simultaneously by multiple control circuits to improve productivity, then the memory throughput is improved, but the peak power consumption becomes unacceptably high
Solution Approach 1:
The patent implements feedback through the arbitration circuit that monitors CE update requests from multiple control circuits and provides acknowledgment signals back to them. The arbitration circuit uses this feedback mechanism to coordinate CE signal updates, ensuring that commands are not executed simultaneously. This feedback-controlled coordination maintains high memory throughput while preventing peak power consumption by staggering command execution timing.
Data Source
AI summary
A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.