Flash Controller Background Command Preemption

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Solution Overview

Problem

The ONFI protocol's inability to interrupt and resume background commands efficiently leads to performance degradation when higher priority foreground commands are received, as background operations are not preempted and completed until foreground commands are finished.

Innovation Solution

A controller that distinguishes between foreground and background commands, allowing foreground commands to be executed without interruption and background commands to be preempted and resumed later, utilizing idle time for background operations, and implementing a split foreground/background protocol to manage parallel bandwidth effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If background commands are executed to completion without interruption, then background operations are reliably completed, but foreground command execution is delayed when background commands are in progress

Engineering Contradiction:

Improvebackground operation completionVSAvoidforeground command delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The system dynamically switches between executing background commands to completion and preempting them for foreground commands based on real-time priority needs. The controller can interrupt an in-progress background command when a foreground command arrives, pause the background command, execute the foreground command, then resume the background command later, making the execution mode flexible rather than fixed

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The command execution is segmented into foreground and background priorities. Background commands are divided into interruptible segments that can be paused and resumed, allowing the system to interleave foreground command execution between background command segments, thereby maintaining both reliability and responsiveness

Inventive Principle:

Principle #1Segmentation

2Reliability

If the controller waits for background commands to complete before processing foreground commands, then background operations finish reliably, but overall system productivity decreases

Engineering Contradiction:

Improvebackground operation completionVSAvoidsystem throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The controller initiates background commands in advance and allows them to proceed concurrently with foreground command processing. By starting background operations preliminarily and allowing them to run in parallel where possible, the system maintains high productivity while still ensuring background operations complete reliably through periodic checks and resumption mechanisms

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system maintains continuous useful action by allowing background commands to execute concurrently with foreground commands whenever resource conflicts don't occur. When conflicts do occur, the background command is paused rather than aborted, preserving its useful action for later resumption, thereby maintaining overall system productivity while ensuring background operation completion

Inventive Principle:

Principle #20Continuity of useful action

3Speed

If background commands are preempted by foreground commands, then foreground command responsiveness improves, but background command execution time increases due to interruptions

Engineering Contradiction:

Improveforeground command responsivenessVSAvoidbackground command execution time

Core Design Contradiction:

SpeedVSDuration of action of moving object

Solution Approach 1:

The controller implements periodic checking and resumption of background commands. Instead of allowing unlimited interruptions that would extend execution time indefinitely, the system uses periodic action patterns where background commands are resumed and allowed to complete in intervals between foreground command batches, thereby limiting the total execution time increase while maintaining foreground responsiveness

Inventive Principle:

Principle #19Periodic action

4Device complexity

If the controller uses a single shared channel for all commands, then device complexity is reduced, but bandwidth utilization efficiency decreases when multiple commands are in progress

Engineering Contradiction:

Improvechannel structureVSAvoidbandwidth utilization

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The single shared channel is segmented into priority lanes for foreground and background commands. The controller divides command processing into distinct foreground and background streams that share the physical channel through time-multiplexed access, maintaining simple hardware while improving bandwidth utilization by preventing background commands from blocking foreground commands

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The channel allocation is dynamic rather than static. The controller dynamically adjusts which command type (foreground or background) gets access to the shared channel based on real-time needs, allowing the single channel to adaptively serve multiple purposes and maximize utilization efficiency without requiring multiple physical channels

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS9229655B2Controller and method for performing background operations

Publication Date: 2016.01.05 SANDISK TECHNOLOGIES LLC

AI summary

The embodiments described herein provide a controller and method for performing a background commands or operations. In one embodiment, a controller is provided with interfaces through which to communicate with a host and a plurality of flash memory devices. The controller contains a processor operative to perform a foreground command received from the host, wherein the processor performs the foreground command to completion without interruption. The processor is also operative to perform a background commands or operations stored in the controller's memory, wherein the processor performs the background command until completed or preempted by a foreground command. If the background command is preempted, the processor can resume performing the background command at a later time until completed.