Flash Memory Controller Command Re-arranging for Parallel Data Bus Optimization
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Solution Overview
Problem
The internal data transfer rate in flash memory systems often lags behind the external data transfer rate, limiting the overall efficiency of storage systems, as existing methods fail to effectively shorten the time required to execute multiple host read commands.
Innovation Solution
A data read method and flash memory controller that configures logical blocks mapped to physical blocks, re-arranges host read commands, and generates a command giving sequence to optimize data input/output operations across multiple data buses, allowing simultaneous reading of data from multiple flash memory modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If multiple host read commands are processed sequentially through a single data bus, then device complexity is reduced, but execution time increases and productivity decreases
Solution Approach 1:
The flash memory controller is divided into multiple independent data input/output buses (first data bus, second data bus, etc.), each capable of simultaneously transferring data between the controller and different flash memory modules. This segmentation allows parallel processing of multiple host read commands, reducing execution time without requiring a single complex centralized processing unit.
Solution Approach 2:
The patent transitions from a single-dimensional sequential processing architecture to a multi-dimensional parallel architecture by introducing multiple data buses operating simultaneously. Each data bus represents an additional dimension of data flow, enabling concurrent read operations across multiple flash memory modules, thereby reducing overall command execution time.
2Productivity
If internal data transfer rate is increased to match external data transfer rate, then productivity improves, but device complexity increases
Solution Approach 1:
The internal data transfer system is segmented into multiple parallel data buses, each handling a portion of the total data flow. This allows the aggregate internal transfer rate to match the high external SATA interface rate without requiring each individual bus to be overly complex, as the complexity is distributed across multiple simpler parallel channels.
Solution Approach 2:
Multiple data buses are merged at the controller level to present a unified high-speed interface to the host system. The combined bandwidth of multiple parallel buses achieves the high internal transfer rate needed to match external SATA speeds, while each individual bus remains relatively simple in design.
3Productivity
If data is read from multiple flash memory modules simultaneously through separate data buses, then execution time of host read commands is reduced, but device complexity increases
Solution Approach 1:
The controller architecture is segmented into multiple independent data buses, each dedicated to communicating with specific flash memory modules. This segmentation enables simultaneous read operations from multiple modules without requiring a single complex arbitration mechanism, as each bus operates semi-independently.
Solution Approach 2:
The controller pre-arranges the mapping between logical blocks and physical blocks across multiple flash memory modules before executing host read commands. This preliminary organization allows the controller to efficiently distribute read requests across multiple data buses without requiring complex real-time decision-making during command execution.
Data Source
AI summary
A data read method for reading data to be accessed by a host system from a plurality of flash memory modules is provided. The data read method includes receiving command queuing information related to a plurality of host read commands from the host system, each of the host read commands is corresponding to one of a plurality of data input/output buses coupled to the flash memory modules. The data read method also includes re-arranging the host read commands and generating a command giving sequence according to the data input/output buses corresponding to the host read commands. The data read method further includes sequentially receiving and processing the host read commands from the host system according to the command giving sequence and pre-reading data corresponding to a second host read command. Thereby, the time for executing the host read commands can be effectively shortened.