Flash Controller Hardware Copy-Back Speed

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Solution Overview

Problem

Conventional flash memory devices are limited by the time required to perform operations such as copy-back and merge operations, which are typically handled by firmware, leading to reduced operating speed as storage capacity increases.

Innovation Solution

A flash memory system that performs copy-back program operations in hardware using a flash controller with address and control registers, allowing for faster execution of these operations without software or firmware intervention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If copy-back program operations are performed using firmware, then the memory device can handle complex operations with flexibility, but the operating speed decreases and time consumption increases

Engineering Contradiction:

Improveoperational flexibilityVSAvoidoperating speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent divides the control functionality into two segments: firmware handles high-level command interpretation and configuration, while hardware circuits execute specific copy-back and merge operations. This segmentation allows firmware to maintain flexibility in operation selection while hardware provides high-speed execution of routine tasks.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces hardware control circuits as an intermediary between the firmware and memory arrays. These circuits receive control signals from firmware and automatically perform copy-back and merge operations, acting as a mediator that translates flexible firmware commands into high-speed hardware actions.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If storage capacity of flash memory is increased, then more data can be stored, but the time required for copy-back and merge operations increases when using firmware

Engineering Contradiction:

Improvestorage capacityVSAvoidoperation time

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The patent implements self-service hardware circuits that automatically perform copy-back and merge operations without requiring continuous firmware intervention. The hardware monitors memory status and autonomously executes operations based on pre-configured parameters, reducing the time burden that would otherwise scale with storage capacity.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent enables continuous hardware-based operation execution for copy-back and merge tasks. Once initiated by firmware, these operations proceed continuously through dedicated hardware circuits without interruption or re-processing, maintaining constant operational throughput regardless of data volume.

Inventive Principle:

Principle #20Continuity of useful action

3Reliability

If firmware is used to control internal operations, then comprehensive control and error handling are achieved, but the overall performance and throughput of the memory device are limited

Engineering Contradiction:

Improvecontrol reliabilityVSAvoidmemory throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent replaces the software-based firmware control mechanism with hardware-based control circuits for specific operations. This substitution eliminates the interpretation and execution overhead inherent in firmware, providing more reliable and deterministic control for time-critical copy-back and merge operations while maintaining overall system reliability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS7941586B2Flash memory device and memory system controlling a copy-back program operation in hardware

Publication Date: 2011.05.10 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory system comprises a flash memory, a processing unit, and a flash controller including address and control registers, the address and control registers being configured to receive information from the processing unit, wherein the flash controller is configured to control a copy-back program operation of the flash memory in hardware based on information stored in the address and control registers.