Flash Controller Fetch Integrity via CRC Verification

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Solution Overview

Problem

Execute-in-Place (XiP) systems face errors in fetching instructions from Flash memory due to high-frequency fetching, high temperature and pressure, or electromagnetic interferences, leading to logical errors and system crashes.

Innovation Solution

A method involving a Flash controller that converts virtual read addresses to physical read addresses, reads instructions to a FIFO storage, calculates and compares CRC codes to verify the integrity of the fetch process, ensuring successful instruction retrieval.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If instructions are fetched directly from Flash memory in XiP systems, then memory access speed is improved and system complexity is reduced, but error rate increases due to high-frequency fetching, high temperature and pressure, or electromagnetic interferences

Engineering Contradiction:

Improvememory access speedVSAvoidfetch accuracy

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing a first CRC code along with the instructions in the Flash memory before fetching. This allows the system to verify fetch accuracy immediately after retrieval by comparing it with a second CRC code calculated from the fetched instructions, without needing to re-fetch or re-verify multiple times.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by calculating a second CRC code from the fetched instructions and comparing it with the pre-stored first CRC code. This feedback mechanism confirms whether the fetch process was successful and detects any errors caused by high-frequency fetching, temperature, pressure, or electromagnetic interferences, allowing the system to handle errors appropriately.

Inventive Principle:

Principle #23Feedback

2Reliability

If CRC verification is performed on every fetch operation, then fetch accuracy is improved and errors are detected, but processing time increases

Engineering Contradiction:

Improvefetch accuracyVSAvoidprocessing time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent minimizes time loss by performing the computationally intensive first CRC calculation in advance during the write operation and storing it with the instructions. During fetch operations, only a quick comparison with the pre-calculated first CRC code is needed, rather than performing full verification calculations each time.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent replaces complex verification mechanics by using CRC codes as a simplified verification mechanism. Instead of complex error detection methods, the system uses efficient cyclic redundancy check calculations that can be performed quickly with hardware support, reducing the time overhead of verification.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12326814B1Systems and methods for fetching and writing instructions to memory

Publication Date: 2025.06.10 BEKEN CORP

AI summary

A fetch process for a computing system is described herein. The computing system comprises a non-transitory memory. In the non-transitory memory, instructions are stored in Cycle-Redundancy Blocks (CRC blocks). Each of these CRC blocks comprises a first CRC code associated with the instructions stored in the CRC block. During a fetch process, the computing system generates a second CRC code based on the instructions stored in the CRC block and compares the second CRC code with the first CRC code to ascertain the success of the fetch process.