Flash Memory Controller Deleted Address Management
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Solution Overview
Problem
Flash memory storage systems face inefficiencies in write speed and data management due to the inability to accurately identify deleted data, leading to unnecessary maintenance of physical blocks that have been deleted by the host system.
Innovation Solution
A flash memory controller and data processing method that identifies deleted logical addresses and marks corresponding physical addresses as invalid, allowing the system to differentiate between stored and deleted data, thereby optimizing data management and write efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the flash memory controller maintains all physical blocks including deleted data, then data reliability is ensured, but write speed and efficiency deteriorate due to unnecessary maintenance operations
Solution Approach 1:
The patent extracts deleted logical addresses from the total address space and separates them into a dedicated deleted address space. This allows the flash memory controller to ignore and exclude deleted data from maintenance operations, thereby improving write speed while maintaining reliability through the mapping relationship between logical and physical addresses.
Solution Approach 2:
The patent segments the address space into valid logical addresses and deleted logical addresses. By dividing the address space, the controller can selectively manage only valid addresses for writing operations while maintaining the mapping information for deleted addresses to ensure data reliability, thus resolving the contradiction between reliability and write speed.
2Ease of operation
If the host system deletes data by updating file system space information only, then ease of operation is improved, but the flash memory controller cannot identify deleted data leading to inefficient data management
Solution Approach 1:
The patent implements a feedback mechanism where the host system's file system space information updates are reflected in the flash memory controller's deleted address space. This feedback loop allows the controller to identify deleted data and adjust its management operations accordingly, improving data management efficiency while maintaining the simple delete operation from the host system's perspective.
3Reliability
If the flash memory controller erases entire physical blocks containing old data, then data reliability is maintained, but loss of time increases due to unnecessary erasure operations on already deleted data
Solution Approach 1:
The patent performs preliminary action by pre-identifying deleted logical addresses through the mapping relationship before initiating physical erasure operations. This allows the controller to target only physical blocks containing valid data for erasure, avoiding unnecessary time-consuming operations on blocks with already deleted data while maintaining data reliability.
Data Source
AI summary
A flash memory storage system including a flash memory chip, a connector, and a flash memory controller is provided. The flash memory controller configures a plurality of logical addresses and maps the logical addresses to a part of the physical addresses in the flash memory chip, and a host system uses a file system to access the logical addresses. Besides, the flash memory controller identifies a deleted logical address among the logical addresses and marks data in the physical address mapped to the deleted logical address as invalid data.