Flash Memory Controller Parallel Initialization With Empty-Page Detection
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Solution Overview
Problem
Portable memory devices with MLC flash memories face instability issues, leading to delayed initialization and prolonged boot-up times in electronic devices due to inadequate access control mechanisms.
Innovation Solution
A method involving a controller with sub-circuits for parallel processing, including a randomizing/de-randomizing and ECC circuit, and an empty-page detection circuit, to accelerate initialization by performing de-randomizing, ECC decoding, and empty-page detection on data streams from non-volatile memory, allowing early access to storage space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC flash memory is used to increase storage capacity and reduce cost, then recording density is improved, but initialization time increases due to instability issues
Solution Approach 1:
The patent applies preliminary action by performing empty-page detection on predetermined blocks before the main initialization process. The controller detects empty pages in advance during a preliminary scanning phase, identifies valid data locations, and prepares initialization information beforehand. This allows the boot-up process to skip unnecessary initialization steps for empty blocks, significantly reducing initialization time while maintaining the high recording density of MLC flash memory
2Reliability
If initialization of memory device is completed before electronic device can use storage space, then data access control is ensured, but boot-up period is prolonged
Solution Approach 1:
The controller performs preliminary detection of empty pages and preparation of initialization information before the electronic device needs to access storage space. By identifying which blocks are already empty and which contain valid data during the boot-up process, the system can skip unnecessary initialization steps, reducing boot-up period while maintaining reliable data access control through the controller's management mechanisms
Solution Approach 2:
The patent segments the initialization process by dividing blocks into predetermined blocks that are scanned separately. The controller processes blocks in segments, detecting empty pages in each segment independently, and uses this segmented information to optimize the initialization sequence. This segmentation allows parallel processing and reduces the overall boot-up period while ensuring each segment's data access control requirements are met
3Productivity
If parallel processing is performed using sub-circuits, then initialization speed is improved, but device complexity increases
Solution Approach 1:
The controller is segmented into specialized sub-circuits, each dedicated to a specific function: empty-page detection circuit, de-randomizing circuit, and ECC decoding circuit. This segmentation enables parallel processing where multiple operations occur simultaneously on different blocks, significantly improving initialization speed. The modular architecture manages complexity by assigning specific tasks to dedicated circuits rather than using a single general-purpose processor
4Productivity
If empty-page detection is performed to accelerate initialization, then productivity is improved, but measurement precision requirements increase
Solution Approach 1:
The patent replaces complex full initialization and verification processes with a simpler empty-page detection mechanism that examines specific page indicators. Instead of performing complete data validation to ensure precision, the system uses a lightweight detection circuit that checks page status bits to identify empty pages with high accuracy. This substitution maintains sufficient detection precision while dramatically improving initialization speed by avoiding unnecessary full-verification steps
Data Source
AI summary
A method for controlling operations of a memory device, the memory device and controller thereof, and an associated electronic device are provided. The method may include: transmitting a read command to a non-volatile (NV) memory to make the NV memory output a data stream; and utilizing a plurality of sub-circuits of a control logic circuit of the controller to perform parallel processing upon the data stream, respectively. Utilizing the sub-circuits to perform parallel processing upon the data stream may include: utilizing a randomizing/de-randomizing and error correction code (ECC) circuit to perform de-randomizing and ECC decoding according to the data stream, wherein this operation is related to initialization of the memory device; and utilizing an empty-page detection circuit to perform empty-page detection according to the data stream, wherein this operation is related to speeding up of the initialization of the memory device.


