Flash Memory Controller Fast Erase Mode
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Solution Overview
Problem
Traditional flash memory erase processes are time-consuming, taking up to 87 minutes to erase all blocks in a solid state drive, and are vulnerable to interruption, which can lead to data exposure if power is lost during the process.
Innovation Solution
Implementing a fast erase mode that uses a single high-voltage pulse instead of multiple incremental pulses, allowing for rapid erasure of flash memory blocks by switching the erase mode upon receiving a fast erase signal and verifying the completion of the erase operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional multi-pulse erase mode is used, then data security is improved, but erase time becomes excessively long
Solution Approach 1:
The system dynamically switches between two erase modes (first erase mode with multiple pulses and second erase mode with single pulse) based on received signals. The controller can adaptively select the appropriate erase strategy, allowing the erase process to be flexible and responsive to different operational requirements, thus resolving the contradiction between security and speed.
Solution Approach 2:
The patent changes the erase operation parameters by introducing a second erase mode that uses a single pulse with potentially different voltage characteristics compared to the traditional multi-pulse mode. By modifying the pulse configuration parameters, the system achieves faster erasure while maintaining data security through verification mechanisms.
2Manufacturing precision
If traditional multi-pulse erase process is used, then thorough erasure is achieved, but vulnerability to interruption increases
Solution Approach 1:
The verification step is performed immediately after the erase operation (whether single-pulse or multi-pulse) to confirm successful erasure before the system returns to idle state. This preliminary verification action ensures that even if the process is interrupted, the system can detect incomplete erasure and respond appropriately, thus improving interruption resistance while maintaining erasure completeness.
Solution Approach 2:
The system implements a feedback mechanism through verification operations that check whether erasure was successful. Based on the verification result, the system can determine if additional erasure cycles are needed or if the operation can be considered complete. This feedback loop enhances both erasure completeness and resistance to interruption.
3Productivity
If fast erase mode with single pulse is used, then erase speed is improved, but risk of incomplete erasure increases
Solution Approach 1:
The verification operation serves as a feedback mechanism that confirms whether the single-pulse erasure was successful. If verification fails, the system can initiate additional erasure cycles or switch to the multi-pulse mode to ensure complete erasure, thus maintaining reliability while benefiting from the speed improvement of the single-pulse approach.
Solution Approach 2:
The verification step is executed immediately after the single-pulse erasure to preliminarily confirm success before considering the operation complete. This preliminary check ensures that the fast erase mode does not compromise erasure completeness, as any incomplete erasures can be detected and corrected.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces erase time by up to a factor of twenty, ensuring secure and efficient data deletion, even under stressful conditions, without causing long-term damage to the memory cells.
Implementation Method 1
When the cell is erased, the electrons in the floating gate are removed by quantum tunneling (a tunnel current) from the floating gate to, for example, the source and/or substrate.
Data Source
AI summary
A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a plurality of erase pulses and a second erase mode for erasing the one or more groups of flash memory cells using a single erase pulse. The controller may receive a fast erase signal to erase the one or more groups of flash memory cells and, in response to the signal, switch operating parameters of the flash memory device from first parameters corresponding to the first erase mode to second parameters corresponding to the second erase mode, and instruct the flash memory device to perform an erase operation on the one or more groups of flash memory cells according to the second parameters. The controller may then verify that the erase operation was completed using the single erase pulse.