Flash Controller Hexadecimal Address Translation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing flash translation layer in memory systems faces high workload due to the traditional binary notation system for address translation, which requires extensive bit calculations and increases the complexity of accessing memory blocks across multiple channels.
Innovation Solution
A controller is designed with a central processing unit that generates commands and manages logical addresses using a hexadecimal notation system, reducing the workload by omitting the need for physical address translation and utilizing a flash interface layer to queue commands based on channel workloads, translating logical addresses into physical addresses efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the traditional binary notation system is used for address translation in the flash translation layer, then the address translation can be performed, but the workload of the flash translation layer becomes high due to extensive bit calculations
Solution Approach 1:
The patent changes the notation system parameter from binary to hexadecimal, which reduces the number of bits required to represent addresses. This parameter change directly reduces the computational complexity and workload of the flash translation layer while maintaining address translation functionality.
Solution Approach 2:
The patent extracts the address translation function from the flash translation layer and relocates it to the flash interface layer. This separation removes the computational burden from the flash translation layer, improving its productivity while maintaining the necessary translation capability in the flash interface layer.
2Measurement precision
If the flash translation layer performs physical address translation, then accurate address mapping is achieved, but the number of bits required for address representation increases
Solution Approach 1:
The patent changes the address representation parameter from binary to hexadecimal notation. This change reduces the quantity of bits required to represent the same address space while maintaining precise address mapping through the flash interface layer's translation function.
3Adaptability or versatility
If the flash translation layer manages address translation across multiple channels, then comprehensive memory block access is enabled, but the workload and complexity increase
Solution Approach 1:
The patent extracts the channel management and address translation functions from the flash translation layer and places them in the flash interface layer. This separation enables multi-channel access capability while reducing the complexity burden on the flash translation layer.
Solution Approach 2:
The patent segments the controller functions into distinct layers: the flash translation layer handles high-level address management, while the flash interface layer handles channel-specific translation and command queuing. This segmentation distributes complexity across multiple specialized components.
Data Source
AI summary
Provided herein may be a controller and a method of operating the controller. The controller may include a central processing unit configured to generate a command, manage a logical address using a notation system, a radix of which is greater than that of a binary notation system, and output the command and the logical address, and a flash interface layer configured to queue the command depending on workloads of dies, translate the logical address into a physical address, and output the command and the physical address through a selected channel.