Flash Memory Controller Inverting Circuit for Erase Error Correction

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Solution Overview

Problem

Error-correcting modules in flash memory systems incorrectly determine parity errors after an erase operation due to all 0xFF data and error-correcting codes, leading to failed reading operations.

Innovation Solution

Incorporating a first inverting circuit in the controller to invert all 0xFF data and error-correcting codes into all 0x00 before performing error-correcting operations, preventing wrong determinations by the error-correcting module.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error-correcting codes are provided to maintain data completeness, then data reliability is improved, but wrong error determination occurs after erase operation

Engineering Contradiction:

Improvedata completenessVSAvoiderror detection accuracy

Core Design Contradiction:

ReliabilityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by inverting the data and error-correcting codes before they are processed by the error-correcting module. This pre-inversion transforms the all-0xFF erased data into a state that the error-correcting module can correctly interpret, preventing wrong error determination from occurring in the first place

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the parameter state of the data by inverting the bit values. When data is erased (all 0xFF), the inverting circuit changes this parameter state to all-0x00 before error correction processing, allowing the error-correcting module to correctly identify that no errors exist rather than falsely detecting parity errors

Inventive Principle:

Principle #35Parameter changes

2Ease of operation

If erase operation converts data to all 0xFF values, then storage readiness is improved, but error-correcting module incorrectly detects parity errors

Engineering Contradiction:

Improvestorage readinessVSAvoidreading operation success

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The inverting circuit performs a preliminary action on the erased data by inverting the all-0xFF values to all-0x00 before the error-correcting module processes them. This pre-processing step ensures that the error-correcting module receives data in a state that prevents incorrect parity error detection, thereby ensuring reading operation success

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The inverting circuit acts as an intermediary between the erase operation and the error-correcting module. It receives the all-0xFF erased data, transforms it by inverting the bits, and passes the transformed data to the error-correcting module, thereby mediating the conflict between erase readiness and error detection accuracy

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS7949929B2Controller and storage device having the same

Publication Date: 2011.05.24 PHISON ELECTRONICS

AI summary

A controller for controlling an access of a non-volatile memory having an error-correcting code area and a data area is provided. The controller includes an error-correcting module and a first inverting circuit electrically connected to the error-correcting module for inverting data and error-correcting codes corresponding to the data. When the controller both writes all 0xFF data in the data area and writes all 0xFF error-correcting codes in the error-correcting code area, the first inverting circuit inverts the all 0xFF data and the all 0xFF error-correcting codes into all 0x00 data and all 0x00 error-correcting codes, respectively.