Flash Memory Controller LDPC Bit-Flipping With Syndrome Thresholds
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Solution Overview
Problem
Conventional bit-flipping LDPC decoders face challenges in enhancing decoding performance and correction rate while maintaining low power consumption, due to limitations in data transmission per codeword bit.
Innovation Solution
A memory controller with a variable-node circuit and check-node circuit that executes a configurable decoding strategy, determining a syndrome weight and flipping strategy to flip codeword bits, thereby improving decoding performance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bit-flipping LDPC decoder limits data transmission to one bit per codeword bit per iteration, then power consumption is reduced, but decoding performance and correction rate cannot be improved
Solution Approach 1:
The patent implements a dynamic bit-flipping mechanism where the number of bits flipped per codeword bit varies based on syndrome weight thresholds. The system transitions from static single-bit flipping to dynamic multi-level flipping (1 bit, 2 bits, or 3 bits), allowing adaptive adjustment of data transmission volume according to decoding needs while managing power consumption efficiently
Solution Approach 2:
The patent changes the parameter of data transmission volume by introducing syndrome weight-based threshold comparisons. Instead of fixed one-bit transmission, the system varies the number of bits transmitted (1, 2, or 3 bits) based on whether syndrome weights fall below, between, or above predetermined thresholds, thereby improving decoding performance without excessive power consumption
2Reliability
If more bits are transmitted per codeword bit during each iteration, then decoding performance and correction rate improve, but power consumption increases
Solution Approach 1:
The patent implements parameter changes by varying the data transmission volume (number of bits) based on syndrome weight thresholds. The system dynamically adjusts between transmitting 1, 2, or 3 bits per codeword bit according to decoding progress, achieving improved correction rates while controlling power consumption through conditional multi-level flipping
Solution Approach 2:
The system employs dynamic adjustment of bit-flipping intensity based on real-time syndrome weight evaluation. By making the data transmission volume adaptive rather than fixed, the system optimizes the balance between correction rate improvement and power consumption, flipping more bits only when syndrome weights indicate higher error probability
Data Source
AI summary
A memory controller for use in a data storage device is provided. The memory controller includes a variable-node circuit and a check-node circuit. The check-node circuit is configured to obtain a codeword difference from the variable-node circuit, and calculate a syndrome according to the codeword difference. During each LDPC (low-density parity check) decoding iterative operation, the variable-node circuit executes the following steps: determining syndrome weight according to a channel value and the syndrome from the check-node circuit; obtaining a previous codeword generated by a previous LDPC decoding iterative operation; determining a flipping strategy of a bit-flipping algorithm for each codeword bit in the previous codeword according to the syndrome weight and a predetermined threshold, and flipping one or more codeword bits in the previous codeword according to the flipping strategy to generate an updated codeword; and subtracting the previous codeword from the updated codeword to generate the codeword difference.