Flash Controller Logical Address Consolidation for Data Relocation

Solution Overview

Problem

Flash storage devices face performance and power consumption issues during data relocation due to the time-consuming and power-intensive process of scanning every flash management unit (FMU) for metadata, especially in jumbo blocks spanning multiple physical blocks across dies or planes.

Innovation Solution

The controller consolidates logical addresses in volatile memory and stores them in a reduced number of FMUs, allowing for fewer page reads during relocation by reading only the pages containing consolidated logical addresses, thereby reducing the number of FMUs that need to be scanned.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If the flash storage device scans every FMU in the block for metadata during data relocation, then complete metadata information is obtained, but relocation time and power consumption increase significantly

Engineering Contradiction:

Improvemetadata completenessVSAvoidrelocation time

Core Design Contradiction:

Loss of informationVSLoss of time

Solution Approach 1:

The controller performs preliminary actions by consolidating logical addresses into volatile memory before the relocation process begins. This pre-consolidation ensures that when relocation occurs, the controller only needs to read from a reduced number of FMUs containing consolidated addresses, rather than scanning every FMU in the block, thus significantly reducing relocation time while maintaining metadata completeness

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Volatile memory serves as an intermediary between the flash memory blocks and the controller's relocation processing. Logical addresses are first consolidated into volatile memory, which acts as a temporary storage and indexing structure. This intermediary allows the controller to efficiently locate and read only the necessary FMUs during relocation, avoiding the need to scan all FMUs while ensuring complete metadata information is obtained

Inventive Principle:

Principle #24Intermediary (Mediator)

2Loss of information

If the flash storage device scans every FMU in the block for metadata during data relocation, then complete metadata information is obtained, but power consumption increases significantly

Engineering Contradiction:

Improvemetadata completenessVSAvoidpower consumption

Core Design Contradiction:

Loss of informationVSUse of energy by moving object

Solution Approach 1:

The controller performs preliminary actions by consolidating logical addresses into volatile memory before the relocation process begins. This pre-consolidation ensures that when relocation occurs, the controller only needs to read from a reduced number of FMUs containing consolidated addresses, rather than scanning every FMU in the block, thus significantly reducing relocation time while maintaining metadata completeness

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Volatile memory serves as an intermediary between the flash memory blocks and the controller's relocation processing. Logical addresses are first consolidated into volatile memory, which acts as a temporary storage and indexing structure. This intermediary allows the controller to efficiently locate and read only the necessary FMUs during relocation, avoiding the need to scan all FMUs while ensuring complete metadata information is obtained

Inventive Principle:

Principle #24Intermediary (Mediator)

3Loss of information

If logical addresses are stored individually in each FMU header, then each FMU has complete address information, but the number of FMUs to be scanned during relocation increases

Engineering Contradiction:

Improveaddress information completenessVSAvoidnumber of FMUs to scan

Core Design Contradiction:

Loss of informationVSQuantity of substance

Solution Approach 1:

The controller merges multiple logical addresses into a single consolidated address structure stored in one or more FMUs. Instead of having individual FMU headers each containing complete address information for every FMU in the block, the controller consolidates these addresses and stores them in a reduced number of FMUs. This merging approach maintains complete address information while significantly reducing the quantity of FMUs that need to be scanned during relocation operations

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11934706B2Smart relocation scan optimization

Publication Date: 2024.03.19 SANDISK TECHNOLOGIES LLC

AI summary

Aspects of a storage device provide an optimized data relocation scanning process which significantly reduces a number of page reads performed during a block relocation scan by consolidating logical addresses for multiple FMUs in a single FMU. The storage device includes a memory comprising a block including pages and FMUs, and a controller that is configured to store, in one of the FMUs, logical addresses for multiple FMUs. The controller is further configured, in response to a data relocation command, to read the logical addresses from the FMU, to determine at least one of the read logical addresses is mapped to a current FMU in a L2P mapping table, and to relocate data stored at the valid logical addresses in response to the determination. As a result, latency and power consumption associated with data relocation may be significantly reduced and storage device performance may thus be improved.