Flash Controller Merged Background Management Process

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Solution Overview

Problem

As flash memory technologies advance with increasing cell densities, they become more prone to bit errors, necessitating increased discrete flash management functions and processing, which can compromise efficiency and reliability.

Innovation Solution

Implementing a merged background management process in a flash memory controller that iteratively performs read sweeps across page groups to record error statistics and employs these statistics in other background management functions, enhancing processing and data efficiencies without sacrificing system-level reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If discrete flash management functions are implemented to address bit errors in high-density flash memory, then reliability is improved, but device complexity and processing overhead increase

Engineering Contradiction:
Improvesystem-level reliabilityVSAvoidnumber of discrete flash management functions
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple discrete background flash management functions (read sweeping, wear leveling, calibration) into a single merged background management process. The controller performs a read sweep of page groups and uses the collected error statistics to drive multiple management functions simultaneously, eliminating the need for separate discrete functions and reducing overall system complexity while maintaining reliability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The merged background management process serves multiple purposes: it performs error detection through read sweeping, monitors wear characteristics for wear leveling decisions, and collects calibration data for threshold voltage adjustments. This single multi-functional process replaces what were previously separate specialized functions, reducing device complexity while improving reliability through coordinated error handling

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple discrete flash management functions are implemented, then bit error handling is improved, but processing efficiency deteriorates

Engineering Contradiction:
Improvebit error handling capabilityVSAvoidmemory management processing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By merging read sweeping, wear leveling, and calibration into a single background process, the patent eliminates redundant processing. The controller performs one read sweep and reuses the collected error statistics across multiple management functions, rather than performing separate sweeps for each function, thereby improving processing efficiency while maintaining comprehensive bit error handling

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The merged background management process continuously operates as a unified workflow, where error statistics collected during read sweeping are immediately utilized by wear leveling and calibration functions within the same operational cycle. This continuous utilization of collected data without interruption or redundancy improves overall processing efficiency

Inventive Principle:
Principle #20Continuity of useful action

3Quantity of substance

If increasing cell densities are used to improve storage capacity, then cost per byte is reduced, but susceptibility to bit errors increases

Engineering Contradiction:
Improvestorage capacityVSAvoidbit error susceptibility
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The merged background management process continuously collects error statistics from read sweeps and uses this feedback to dynamically adjust wear leveling strategies and calibration parameters. This feedback mechanism allows the system to adapt to the increased bit error susceptibility of high-density cells, maintaining reliability despite higher storage capacity

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system uses its own read sweep operations to collect error statistics that automatically inform wear leveling and calibration decisions. The merged background process serves itself by utilizing the data it collects during normal operation to improve its own management of high-density cells, enabling the system to handle increased bit error susceptibility without external intervention

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10365859B2Storage array management employing a merged background management process
Publication Date: 2019.07.30 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10365859B2 patent drawing
  • US10365859B2 patent drawing
  • US10365859B2 patent drawing

AI summary

In at least one embodiment, a controller of a non-volatile memory array iteratively performs a merged background management process independently of any host system's demand requests targeting the memory array. During an iteration of the merged background management process, the controller performs a read sweep by reading data from each of a plurality of page groups within the memory array and recording page group error statistics regarding errors detected by the reading for each page group, where each page group is formed of a respective set of one or more physical pages of storage in the memory array. During the iteration of the merged background management process, the controller employs the page group error statistics recorded during the read sweep in another background management function.