Flash Memory Controller NCQ Command Sequencing

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Solution Overview

Problem

The existing flash memory systems face inefficiencies in data writing due to the mismatch between high-speed data transmission connectors and low-speed flash memory programming, leading to prolonged response times for host write commands.

Innovation Solution

Implementing a flash memory controller with a native command queuing (NCQ) protocol that sequences host write commands and data, allowing for simultaneous data transfer and programming through cache program commands, utilizing a microprocessor unit, buffer memory, flash memory interface, host interface, and memory management unit to manage data access efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is transferred through high-speed connectors (e.g., SATA at 1.5 Gb/s or 30 Gb/s), then data transmission speed is improved, but flash memory programming speed remains low causing prolonged response times

Engineering Contradiction:
Improvedata transmission speedVSAvoidresponse time for host write commands
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The flash memory controller pre-sequences host write commands using the NCQ protocol before actual data programming begins. By organizing and preparing the command sequence in advance, the controller can efficiently manage the programming process without waiting for each command to be individually processed, thereby reducing the overall response time and better utilizing the high-speed data transmission capability of the connector.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the flash memory module programs data into memory cells, then data is written to storage, but the flash memory controller cannot process next commands during the programming procedure

Engineering Contradiction:
Improvedata writing completionVSAvoidcommand processing throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The flash memory controller segments the data writing process into distinct phases: command sequencing phase (using NCQ to organize multiple commands) and execution phase (programming data into memory cells). This segmentation allows the controller to prepare and queue multiple commands in advance, then execute them systematically, improving command processing throughput while ensuring reliable data writing completion.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The NCQ protocol enables continuous command sequencing and queuing, allowing the flash memory controller to maintain a pipeline of ready-to-execute commands. This continuity ensures that as soon as one programming operation completes, the next command is already prepared and can be immediately executed, maximizing productivity without compromising data writing reliability.

Inventive Principle:
Principle #20Continuity of useful action

3Measurement precision

If the flash memory controller waits for acknowledgment before processing the next command, then command execution accuracy is maintained, but overall system performance cannot be improved

Engineering Contradiction:
Improvecommand execution accuracyVSAvoidsystem performance
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The controller performs preliminary command sequencing and validation using the NCQ protocol before execution begins. By pre-organizing the command sequence and verifying its correctness in advance, the controller ensures accurate command execution while reducing the need for repeated acknowledgment waiting, thereby improving overall system performance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The NCQ protocol implements a feedback mechanism where the controller sequences commands based on expected acknowledgment patterns and command completion status. This structured feedback approach maintains command execution accuracy by verifying each command's completion while enabling efficient batch processing, thus improving productivity without sacrificing precision.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8386699B2Method for giving program commands to flash memory for writing data according to a sequence, and controller and storage system using the same
Publication Date: 2013.02.26 PHISON ELECTRONICS
  • US8386699B2 patent drawing
  • US8386699B2 patent drawing
  • US8386699B2 patent drawing

AI summary

A method for giving program commands to a flash memory chip is provided, the method is suitable for writing data from a host system into the flash memory chip. In the present method, a plurality of host write commands and data corresponding to the host write commands are received from the host system by using a native command queuing (NCQ) protocol, and cache program commands are gived to the flash memory chip to write the data into the flash memory chip. Accordingly, the time for executing the host write commands is effectively shortened by writing the data through the cache program commands and the NCQ protocol.