Flash Memory Controller Parallel Data and Checksum Buffering
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Solution Overview
Problem
Conventional Flash controllers have low efficiency due to serial processing of data blocks, requiring frequent CPU intervention and resulting in increased clock resources and idle hardware usage during write and read operations, which limits data-access performance.
Innovation Solution
Implementing a method where multiple main data blocks are outputted and buffered simultaneously with their checksum data, allowing for concurrent error correction and transmission without waiting for previous blocks to complete, and using a reconfigurable control unit to optimize operations, reducing CPU intervention and improving flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial processing is adopted for each main data block of 512 bytes, then error correction can be performed accurately, but data-access efficiency deteriorates due to frequent CPU intervention and idle hardware usage
Solution Approach 1:
The patent segments the data transmission process into multiple main data blocks that can be processed in parallel. Each block is handled independently through separate processing paths, allowing concurrent error correction operations without blocking other blocks. This segmentation enables the system to maintain reliability through accurate ECC while improving productivity by eliminating serial processing bottlenecks.
Solution Approach 2:
The patent implements preliminary error correction calculations for multiple data blocks before they are fully transmitted or written to memory. The ECC processor performs error correction operations in advance for subsequent blocks while current blocks are being transmitted, reducing CPU intervention time and eliminating idle hardware periods. This preliminary action allows the system to maintain both accuracy and efficiency.
2Device complexity
If serial processing is used for transmitting data blocks, then hardware resources are utilized efficiently, but CPU intervention frequency increases and overall throughput decreases
Solution Approach 1:
The patent ensures continuous useful action by overlapping data transmission with error correction operations. Multiple data blocks are transmitted concurrently while error correction is performed on previous blocks, eliminating idle periods. The ECC processor continuously works on different blocks without interruption, and the memory interface continuously receives data, maintaining steady throughput without requiring CPU intervention for each block.
Solution Approach 2:
The system divides the data stream into independent segments (main data blocks) that can be processed in parallel. Each segment has its own dedicated processing path, allowing simultaneous transmission and error correction operations. This segmentation enables continuous hardware utilization while maintaining high throughput by preventing CPU intervention for each individual block.
3Productivity
If concurrent processing of multiple data blocks is implemented, then data-access efficiency improves, but device complexity increases due to additional buffering and control mechanisms
Solution Approach 1:
The patent implements a universal buffering mechanism that handles multiple data blocks concurrently. The buffer area serves multiple functions: storing current data blocks, buffering error correction codes, and managing parallel processing queues. This multi-functional buffer reduces the need for separate dedicated structures for each processing stage, improving data-access efficiency while limiting the increase in overall device complexity.
Solution Approach 2:
The patent introduces a buffer area as an intermediary between the data transmission interface and the error correction processor. This buffer mediates between concurrent operations, allowing data blocks to be transmitted while error correction is performed on previous blocks. The buffer manages the complexity of concurrent processing by providing a centralized storage and coordination mechanism, improving productivity without proportionally increasing device complexity.
Data Source
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AI summary
An embodiment of the present invention provides a method for controlling access to data in a Flash, including steps as follows: outputting at least one main data block to a buffer area of the Flash continuously, the buffer area of the Flash being adapted to buffer data to be inputted to a storage area of the Flash; generating and buffering checksum data for each main data block while outputting the at least one main data block; and outputting the buffered checksum data of the at least one main data block to the buffer area of the Flash. An embodiment of the present invention also provides another method for controlling access to data in the Flash, apparatuses corresponding to the methods and methods for controlling data access by a controller. Through the technical schemes provided by the embodiments of the present invention, the efficiency of data access in the Flash is raised.