Flash Memory Controller Parallel Block Testing
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Solution Overview
Problem
Conventional flash memory testing methods cannot ensure all physical blocks are thoroughly tested, and the process is time-consuming due to the need for sequential writing and reading operations across multiple flash memory dies.
Innovation Solution
A flash memory controller with a microprocessor unit, flash memory interface unit, host interface unit, and memory cell testing unit that enables simultaneous broadcasting of testing data to and reading from all physical blocks across multiple flash memory dies, allowing for comprehensive testing of all physical blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional sequential testing method is used to write and read testing data across multiple flash memory dies, then the testing process can be performed with simple control logic, but the testing time is excessively long and not all physical blocks can be thoroughly tested
Solution Approach 1:
The flash memory system is segmented into multiple independent dies (first flash memory die, second flash memory die, etc.), each with its own physical blocks that can be tested independently. The controller divides the testing task across these segmented dies, enabling parallel testing operations that dramatically increase testing speed while maintaining manageable control complexity for each individual die.
Solution Approach 2:
The controller merges the testing operations of multiple flash memory dies into a unified parallel testing process. By combining the testing capabilities across first, second, and subsequent flash memory dies, the system achieves comprehensive coverage of all physical blocks simultaneously, resolving the contradiction between thorough testing and testing time.
2Reliability
If host system performs reading and writing test to flash memory storage apparatus, then testing can be performed externally, but the host system cannot access physical blocks in system area and replacement area, resulting in incomplete testing coverage
Solution Approach 1:
The testing functionality is extracted from the host system and embedded directly into the flash memory controller. This extraction enables the controller to directly access and test all physical blocks including those in the system area and replacement area that are normally inaccessible to the host system, achieving complete testing coverage while simplifying the overall operation by making the system self-testable.
Solution Approach 2:
The flash memory controller performs self-testing by directly writing and reading testing data to and from all its physical blocks without requiring host system intervention. This self-service capability ensures complete testing coverage of all areas including system area and replacement area, while maintaining ease of operation through automatic controller-executed testing routines.
Data Source
AI summary
A flash memory controller having a flash memory testing functions is provided, in which the flash memory controller includes a microprocessor unit, a flash memory interface unit, a host interface unit and a memory cell testing unit. The flash memory interface unit is configured for connecting a plurality of flash memory chips, where each flash memory chip has a plurality of flash memory dies and each flash memory die has a plurality of physical blocks. The host interface unit is configured for connecting a host system. The memory cell testing unit is configured for determining whether the physical blocks can be normally written, read and erased. Accordingly, the flash memory controller can perform a flash memory testing under a command of the host system and all the physical blocks of the flash memory chip can be tested during the flash memory testing.