Flash Memory Controller Pin Reduction via Time-Division Multiplexing

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Solution Overview

Problem

Conventional flash memory systems require multiple chip enable pins for accessing multiple flash memory chips, leading to complex control logic and increased chip area, necessitating a solution to control access without increasing the pin count.

Innovation Solution

A memory controller with multiple interfaces, including a host interface and a flash memory device interface, featuring configuration, command control, clock, read command, and data I/O terminals, which allows for device identification, command timing, and data transmission, enabling control of multiple flash memory devices without additional pins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple chip enable pins are used to access multiple flash memory chips, then access control capability is improved, but device complexity and chip area increase

Engineering Contradiction:

Improveaccess control capabilityVSAvoidcontrol logic complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies universality by making the single CE pin perform multiple functions through time-division multiplexing. The pin can enable different flash memory devices at different times based on selection signals from the controller, allowing one pin to replace what would traditionally require multiple pins for accessing multiple devices.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent resolves the contradiction by adding a time dimension to the pin usage. Instead of having multiple pins active simultaneously, the system uses a single pin across multiple time slots, with the controller selecting which device to access at each time period. This transforms a spatial problem (multiple pins) into a temporal solution (time-division multiplexing).

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If multiple chip enable pins are used to access multiple flash memory chips, then access control capability is improved, but chip area increases

Engineering Contradiction:

Improveaccess control capabilityVSAvoidchip area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the functionality of multiple chip enable pins into a single pin by implementing time-division multiplexing. The controller combines the selection logic and timing control to manage access to multiple devices through one shared pin, thereby reducing the total pin count and chip area required.

Inventive Principle:

Principle #5Merging (Combining)

3Device complexity

If sequential access is used in NAND flash I/O interface, then interface simplicity is maintained, but access speed and efficiency deteriorate

Engineering Contradiction:

Improveinterface complexityVSAvoidaccess speed

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent introduces dynamic access patterns that can switch between sequential and parallel modes. The controller can configure the I/O interface to allow parallel reading from multiple flash memory devices simultaneously, improving throughput while maintaining the ability to fall back to sequential access when needed, thus adapting to different performance requirements.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent implements preliminary actions by allowing the controller to prepare and buffer data from multiple flash memory devices before actual data transfer to the host. This pre-fetching and buffering mechanism enables more efficient data retrieval and reduces the impact of sequential access limitations on overall system performance.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS8364881B2Flash memory controller and methods of programming and reading flash memory devices using the controller

Publication Date: 2013.01.29 MARVELL ASIA PTE LTD

AI summary

A system including a plurality of NAND flash memory devices each having a NAND flash interface, where the NAND flash interface of each NAND flash memory device includes an 8-bit data bus, and a memory controller configured to exchange data with the plurality of NAND flash memory devices via the 8-bit data bus. The memory controller is further configured to select a first NAND flash memory device of the plurality of NAND flash memory devices, without using a Chip Enable signal of the NAND flash interface, by transmitting, on the 8-bit data bus, an identification byte identifying the first NAND flash memory device. The memory controller is further configured to transmit, on the 8-bit data bus, a command byte to the first NAND flash memory device. The first NAND flash memory device is configured to perform an operation indicated by the command byte.