Flash Memory Controller Read Command Prioritization
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Solution Overview
Problem
In hybrid data storage apparatuses that combine hard disk drives with NAND flash memory, existing interleaving methods for flash memory control are insufficient to reduce read operation time and enhance reading efficiency due to limitations in simultaneous data transfer across multiple banks.
Innovation Solution
A storage control apparatus with a flash memory controller that prioritizes read-command issuance processing and employs an arbitrator to manage interface buses, allowing independent read access to each bank while minimizing bus conflicts through prioritization of read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the flash memory controller uses interleaving method to simultaneously access multiple banks, then access speed is improved, but read operation time cannot be sufficiently reduced due to sequential processing requirements
Solution Approach 1:
The patent applies preliminary action by performing read-command issuance processing in advance before data transfer. The controller issues read commands to multiple banks sequentially and stores them in a command queue, then executes these pre-issued commands in parallel during data transfer operations. This allows the read operations to be prepared ahead of time and executed concurrently, reducing overall read operation time while maintaining fast access speed.
2Device complexity
If the interface bus is shared among multiple banks, then device complexity is reduced, but bus conflicts occur during simultaneous access to multiple banks
Solution Approach 1:
The controller issues read commands to multiple banks in advance and stores them in a command queue structure. When data transfer occurs, the controller retrieves and executes commands from the queue in parallel, ensuring that bus access is coordinated and conflicts are avoided. This preliminary command issuance and queuing mechanism allows multiple banks to be accessed simultaneously without bus conflicts, maintaining reliability while keeping the interface structure simple.
3Reliability
If read commands are issued sequentially to multiple banks, then bus conflicts are minimized, but idle times in interface bus usage increase
Solution Approach 1:
The patent implements continuous useful action by maintaining a command queue that continuously stores and manages read commands for multiple banks. During data transfer operations, the controller continuously retrieves and executes commands from the queue, ensuring that the interface bus is continuously utilized without idle time. This allows sequential command issuance to be combined with parallel execution, eliminating bus idle time while avoiding conflicts through coordinated command management.
Data Source
AI summary
According to one embodiment, a storage control apparatus includes an interface and a controller. The interface transfers data or a command to or from a nonvolatile memory including a storage area for each of banks. The controller controls read operations for the banks in accordance with generation of access requests to the banks, respectively. The controller prioritizes performing read-command issuance processing included in each of the read operations.