Flash Controller Read Voltage Tuning for Lower SSD Read Latency
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Solution Overview
Problem
Data read latency and instability in SSDs due to variations in threshold voltage of flash memory cells, leading to increased read retries and reduced throughput in information processing.
Innovation Solution
Implementing regular read voltage optimization by reading data from flash memory at predetermined intervals, determining and recording an appropriate read voltage based on the data read, and using queue management to balance data read/write processes with management processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data read is performed at fixed read voltage without optimization, then device complexity is reduced, but data read latency increases due to read retries when threshold voltage varies
Solution Approach 1:
The patent applies preliminary action by performing read voltage optimization at predetermined intervals before actual data read operations. The controller determines and sets an optimized read voltage in advance based on threshold voltage distribution characteristics, so that when data read is needed, the optimal voltage is already in place, avoiding read retries and reducing latency without adding complex real-time control mechanisms
Solution Approach 2:
The patent implements periodic action by optimizing read voltage at predetermined intervals rather than continuously or on every read operation. This periodic optimization balances the need for voltage accuracy with system overhead, maintaining low read latency while avoiding excessive complexity in voltage control mechanisms
2Loss of time
If read voltage optimization is performed frequently, then data read latency is reduced, but productivity decreases due to increased management process overhead
Solution Approach 1:
The patent resolves this contradiction by performing read voltage optimization periodically at predetermined intervals rather than continuously. This ensures that voltage optimization is done frequently enough to maintain low read latency, but not so frequently as to create excessive management overhead that would reduce overall information processing throughput
Solution Approach 2:
The patent applies partial action by optimizing read voltage for specific data blocks at predetermined intervals rather than continuously optimizing all reads. This partial optimization approach reduces the overhead of management processes while still achieving low read latency for the optimized blocks, balancing productivity and response time
3Ease of operation
If threshold voltage variation is not compensated, then ease of operation is maintained, but reliability decreases due to read errors from threshold voltage drift
Solution Approach 1:
The patent applies self-service by having the flash memory controller automatically perform read voltage optimization and threshold voltage compensation without requiring external intervention. The controller autonomously determines optimized read voltages based on threshold voltage distribution and updates them periodically, maintaining both ease of operation and high reliability through automatic adaptation to voltage drift
Solution Approach 2:
The patent implements feedback by using read results to determine and update optimized read voltages. The controller performs read operations, analyzes the results to assess threshold voltage distribution, and adjusts read voltages accordingly. This closed-loop feedback mechanism ensures reliable data reading while maintaining operational simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces data read latency and stabilizes information processing by minimizing read retries and maintaining an optimal balance between data access and management processes.
Implementation Method 1
Data write into a flash memory is performed by accumulating an electric charge according to a write value in the floating gate of each memory cell
Implementation Method 2
At the time of data read, a value is identified on the basis of the magnitude relation between a threshold voltage corresponding to the accumulated electric charge and a read voltage to be applied to the control gate
Data Source
Figure 1
Figure 2(a)~2(d)
Figure 3(a)~3(d)
AI summary
A flash controller of an information processing device regularly implements data read for each of block groups corresponding to ellipses 150, 152, and 154 across channels ch0 to ch3 of a flash memory. Read is tried at varied read voltages until data with an error rate which is equal to or lower than a threshold can be read, and a read voltage that is obtained in the end is stored in the memory. At the time of normal data read, data is read by using a read voltage associated with a target block.