Flash Memory Controller Scheduling for Multi-Interface Parallel Operations
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Solution Overview
Problem
The proliferation of different flash memory device interfaces and protocols poses a challenge for designers of flash controllers, who typically choose one interface and protocol and design the controller accordingly, limiting the ability to support scheduling of parallel operations across multiple channels or flash devices.
Innovation Solution
A scheduling system for a memory controller that includes a scheduler configurable to receive operation requests from multiple masters, form sequences of phases, arbitrate requests using configurable policies, and communicate with flash memory devices having differing interfaces through a scoreboard mechanism, enabling flash memory device-independent commands across multiple channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a flash controller is designed to support one specific flash memory device interface and protocol, then the device complexity is reduced and ease of manufacture is improved, but the adaptability to support multiple different flash memory interfaces and protocols deteriorates
Solution Approach 1:
The flash controller is designed with a universal interface that can support multiple flash memory device interfaces and protocols (asynchronous SDR, synchronous DDR, Toggle Mode, ONFI, etc.). The controller includes a scheduler and sequencer that can dynamically adapt to different protocols, allowing a single device to perform multiple functions and communicate with various flash memory devices without requiring separate dedicated controllers for each protocol type.
Solution Approach 2:
The flash controller is divided into functional modules including a scheduler that receives operation requests from multiple masters, forms sequences of phases, and arbitrates requests using configurable policies. The sequencer is separated as an independent module that receives phases and communicates with flash memory devices through multiple channels. This segmentation allows each module to be optimized independently while maintaining overall versatility.
2Productivity
If a flash controller supports multiple channels and flash devices, then the productivity and parallel operation capability are improved, but the device complexity increases and scheduling difficulty worsens
Solution Approach 1:
The scheduler performs preliminary actions by receiving operation requests from multiple masters, forming sequences of phases from these requests, and arbitrating them using configurable policies before passing them to the sequencer. The scoreboard mechanism tracks the lifetime of operation requests in advance, maintaining state information that enables efficient parallel operation scheduling without increasing real-time decision complexity.
Solution Approach 2:
The scheduler acts as an intermediary between multiple masters and the sequencer, while the sequencer serves as an intermediary between the scheduler and multiple flash memory devices. This layered intermediary structure simplifies the overall system by breaking down complex scheduling decisions into manageable stages, where each intermediary handles specific aspects of the communication and coordination.
3Productivity
If a scheduler arbitrates operation requests from multiple masters through multiple channels, then the parallel operation efficiency is improved, but the difficulty of detecting and measuring system state increases
Solution Approach 1:
The scoreboard mechanism provides feedback by tracking the lifetime of operation requests and maintaining state information about ongoing operations across multiple channels. This feedback enables the scheduler to make informed arbitration decisions and monitor system state without requiring complex external detection mechanisms, as the scoreboard internally maintains visibility into the status of all parallel operations.
Data Source
AI summary
A scheduling system for a memory controller is provided. The system includes a scheduler configurable to receive a plurality of operation requests from a plurality of masters. The scheduler is configurable to form a sequence of one or more phases from each of the operation requests. The scheduler is configurable to arbitrate the plurality of operation requests and the one or more phases through one or more configurable policies. The system includes a sequencer configurable to receive the one or more phases and communicate with at least two flash memory devices having differing types of flash memory device interfaces through a plurality of channels.