Flash Controller Sub-Mapping Table Reduces Host IO Traffic

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Solution Overview

Problem

The existing systems require multiple commands to process contiguous logical block addresses (LBAs) in flash memory, leading to high input/output (IO) traffic between the host and flash memory due to the need for translating each block's physical block address (PBA), especially when regular data access occurs.

Innovation Solution

A method that involves downloading a sub-section of the LBA to PBA mapping table into the flash controller, converting LBAs to PBAs using a sub-mapping table, and initiating direct memory access (DMA) for efficient data transfer between the host and flash memory, reducing the need for multiple commands and IO traffic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple separate commands are issued for each block to process contiguous LBAs, then data can be transferred to flash memory, but the amount of IO traffic between host and flash memory increases significantly

Engineering Contradiction:
Improvedata transfer capabilityVSAvoidIO traffic volume
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent segments the LBA to PBA mapping table into smaller sub-sections that can be independently managed. The flash controller maintains a sub-mapping table that maps a contiguous range of LBAs to PBAs, allowing batch processing of multiple blocks in a single command rather than issuing separate commands for each block, thus reducing IO traffic while maintaining data transfer capability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by pre-loading the LBA to PBA mapping sub-section into the flash controller's sub-mapping table before data transfer operations. This allows the flash controller to perform LBA to PBA translation locally without requiring continuous host intervention and reduces the number of IO commands needed by preparing the mapping information in advance

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If a complete LBA to PBA mapping table is maintained in host memory, then accurate address translation is available, but the host workload and memory requirements increase

Engineering Contradiction:
Improveaddress translation accuracyVSAvoidhost memory burden
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts the LBA to PBA mapping function from the host memory and relocates it to the flash controller by maintaining a sub-mapping table in the flash controller's local memory. This extraction reduces the host's memory burden and processing workload while preserving accurate address translation capability, as the sub-mapping table contains the necessary mapping information for the current data transfer operation

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces the flash controller as an intermediary between the host and flash memory. The flash controller maintains a sub-mapping table that serves as an intermediate structure for LBA to PBA translation. This intermediary approach allows accurate address translation without requiring the host to maintain the complete mapping table in its memory, thereby reducing host complexity and memory requirements

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If LBA to PBA translation is performed for each block individually, then correct physical addresses are obtained, but the time required for data transfer increases

Engineering Contradiction:
Improveaddress mapping accuracyVSAvoiddata transfer time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent merges multiple individual LBA to PBA translation operations into a single batch processing operation. By maintaining a sub-mapping table that contains mappings for multiple contiguous LBAs, the flash controller can translate all addresses in parallel within a single operation, obtaining correct physical addresses for all blocks simultaneously and significantly reducing the time required compared to individual translation of each block

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9858008B2Method to reduce flash memory IOs with host maintained address mapping table
Publication Date: 2018.01.02 SCALEFLUX
  • US9858008B2 patent drawing
  • US9858008B2 patent drawing
  • US9858008B2 patent drawing

AI summary

A system, method and program product for transferring contiguous blocks of data between a host storage and a flash memory. A method is disclosed that includes: receiving from a host at a flash controller a host command that specifies a contiguous set of LBAs and specifies a corresponding sub-section of an LBA to PBA mapping table; fetching the sub-section of the LBA to PBA mapping table from the host and storing the sub-section in a sub-mapping table; and for each LBA in the contiguous set of LBAs, performing a look-up into the sub-mapping table to retrieve a corresponding PBA and using the corresponding PBA to effectuate a data transfer between the host and flash memory from the flash controller.