Flash Memory Controller Table Writing for Power-Loss Accuracy
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Solution Overview
Problem
The erase count mapping table in flash memory devices is prone to distortion due to sudden power offs, leading to inaccurate block erase count tracking and performance degradation, as frequently writing it to the flash memory module affects device efficiency.
Innovation Solution
A control method that dynamically adjusts the frequency of writing the erase count mapping table based on multiple parameters, including erase count sum, wear leveling count sum, maximum erase count difference, power-on count, and write data sum, to minimize distortion and maintain performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the erase count mapping table is frequently written into the flash memory module, then the accuracy of block erase count tracking is improved, but the overall performance of the memory device deteriorates
Solution Approach 1:
The patent implements dynamic write frequency adjustment for the erase count mapping table based on multiple parameters including power-on count, erase count sum, wear leveling count sum, maximum erase count difference, and write data sum. The controller adaptively determines the optimal write frequency to balance accuracy and performance, transitioning from static periodic writing to dynamic condition-based writing.
Solution Approach 2:
The patent changes the writing parameters of the erase count mapping table by introducing a multi-parameter decision mechanism. Instead of using a fixed writing interval, the system evaluates multiple parameters (power-on count, erase count sum, wear leveling count sum, maximum erase count difference, write data sum) to dynamically adjust writing frequency, thereby optimizing both accuracy and performance.
2Productivity
If the erase count mapping table is written less frequently, then the overall performance of the memory device is maintained, but the distortion of the erase count mapping table due to sudden power offs increases
Solution Approach 1:
The patent implements a feedback mechanism where the controller continuously monitors multiple parameters (power-on count, erase count sum, wear leveling count sum, maximum erase count difference, write data sum) and uses this feedback to dynamically adjust the write frequency of the erase count mapping table, ensuring reliability while maintaining performance.
Solution Approach 2:
The patent takes preliminary action by proactively writing the erase count mapping table to flash memory based on predicted risk conditions. When parameters indicate high risk of data loss (e.g., high power-on count with low erase count sum, or large maximum erase count difference), the system performs preliminary writes before potential failures occur, preventing distortion without requiring continuous writing.
3Reliability
If the erase count mapping table is often updated due to block erasure, then the wear leveling function is improved, but the loss of time for writing operations increases
Solution Approach 1:
The patent implements periodic writing of the erase count mapping table based on evaluated conditions rather than continuous writing. The system periodically assesses multiple parameters and performs writes only when necessary, reducing unnecessary write operations and time loss while maintaining wear leveling effectiveness.
Data Source
AI summary
A control method of a memory device includes: updating a wear leveling related data temporarily stored in a buffer memory; obtaining multiple parameters; determining a write frequency according to the multiple parameters; and copying the wear leveling related data from the buffer memory to a flash memory module included in the memory device according to the write frequency.