Adaptive Flash Converter Capacitance Reduction for Low Distortion
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Solution Overview
Problem
Delta-sigma analog-to-digital converters face challenges in balancing stable input range and noise shaping, leading to increased total harmonic distortion and noise, especially when the input signal exceeds a certain threshold, causing unpredictable behavior and potential oscillation.
Innovation Solution
A capacitance reduction circuit that dynamically enables or disables switched capacitor summing circuits based on the comparison of digital code bits with boundary codes, reducing capacitive loading and improving harmonic distortion and noise performance by selectively sampling only necessary bits during high-amplitude signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If noise shaping is increased to attenuate quantization noise in the frequency band of interest, then signal-to-noise ratio is improved, but total harmonic distortion increases and stable input range decreases
Solution Approach 1:
The patent applies dynamics by making the capacitive load adaptive rather than fixed. The switched-capacitor summing circuits are dynamically enabled or disabled based on the amplitude of the input signal, allowing the system to optimize between noise shaping and harmonic distortion performance in real-time. This resolves the contradiction by enabling the system to have both low noise and low distortion depending on operating conditions.
Solution Approach 2:
The patent changes the capacitive load parameter dynamically based on signal amplitude. By adjusting the effective capacitance value according to the input signal level, the system can optimize the trade-off between noise shaping effectiveness and total harmonic distortion, resolving the contradiction between these two performance metrics.
2Manufacturing precision
If switched capacitor summing circuits are always enabled to maintain linearity, then total harmonic distortion is reduced, but capacitive loading increases and settling time worsens
Solution Approach 1:
The patent applies partial action by enabling only the necessary number of switched-capacitor summing circuits based on signal amplitude. Instead of always enabling all circuits, the system enables only enough circuits to handle the current signal level, reducing capacitive loading and settling time while maintaining sufficient linearity for the operating condition.
Solution Approach 2:
The system dynamically adjusts the number of active summing circuits based on signal amplitude, making the capacitive load adaptive. This resolves the contradiction by allowing the system to have low settling time for small signals while maintaining adequate linearity through selective circuit activation.
3Adaptability or versatility
If all quantization circuits are enabled to handle high-amplitude signals, then stable input range is maintained, but power consumption increases and total harmonic distortion worsens
Solution Approach 1:
The patent makes the quantization circuits adaptive by dynamically enabling or disabling them based on signal amplitude. This allows the system to maintain adequate input range while reducing total harmonic distortion by only activating the necessary number of circuits for the current signal level, avoiding the penalties of having all circuits always enabled.
Solution Approach 2:
The patent applies local quality by having different numbers of quantization circuits active in different operating regions. Instead of uniform circuit activation across all signal levels, the system tailors the active circuit configuration to the local signal amplitude, optimizing performance for each operating region.
Data Source
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AI summary
A capacitance reduction circuit retains a conversion digital code of a previous sampling of an input signal of a delta-sigma modulated ADC and compares a set of least significant data bits and most significant bits of the conversion digital code to a least significant and a most significant boundary codes. When the least significant bits of the conversion digital code are less than or equal to the least significant boundary code or when the most significant bits of the conversion digital code are greater than or equal to the most significant boundary code, the capacitance reduction circuitry generates a capacitance reduction enable/disable code applied to multiple summation-quantization circuits to enable or disable groups of the multiple summation-quantization circuits bits to reduce capacitive loading of the outputs of delta-sigma modulator and an input signal to improve the total harmonic distortion and noise.