Flash Wear Leveling Without Translation Tables
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Solution Overview
Problem
Existing flash memory controllers face processing overhead issues when handling sequential data streams due to the use of translation tables for wear leveling, leading to reduced performance and potential buffer overflow, especially in applications like black box recorders that require continuous data recording.
Innovation Solution
Implementing a write counter mechanism that selects recording segments based on data write counters to distribute program/erase cycles evenly across memory blocks, eliminating the need for a translation table and improving sustained write performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If translation tables are used for wear leveling in flash memory controllers, then data can be stored in non-volatile memory, but processing overhead increases and write performance decreases
Solution Approach 1:
The patent extracts and eliminates the translation table component from the wear leveling mechanism. Instead of using complex translation tables to map logical addresses to physical addresses, the invention directly writes data to physical addresses selected by a pseudo-random number generator, removing the source of processing overhead while preserving wear leveling functionality through distributed write operations
2Reliability
If translation tables are used for wear leveling, then data can be stored in non-volatile memory, but power consumption increases
Solution Approach 1:
The patent removes the translation table maintenance and lookup operations that consume significant power in the controller. By replacing this with a pseudo-random number generator that directly selects physical addresses, the system achieves wear leveling with substantially reduced power consumption while maintaining data storage reliability
3Reliability
If translation tables are used for wear leveling, then data can be stored in non-volatile memory, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the complex translation table data structure and associated management logic from the controller. The simplified approach uses a pseudo-random number generator to directly select physical addresses for data writing, dramatically reducing controller complexity while maintaining wear leveling effectiveness through uniform distribution of write operations across memory blocks
Solution Approach 2:
The system uses a pseudo-random number generator that operates autonomously to select physical addresses without requiring complex controller intervention. This self-service mechanism automatically distributes writes across the memory space, reducing the burden on the controller and simplifying the overall system architecture
Data Source
AI summary
A memory system has a controller (e.g., CPU, FPGA, or GPU) and recording segments in a non-volatile memory (e.g., a flash memory device) used by the controller to store data. The controller is configured to: maintain data write counters for the recording segments; select a first segment of the recording segments for recording data from a host system, wherein selecting the first segment comprises scanning the data write counters to identify a first data write counter corresponding to the first segment; receive, from the host system, data to be recorded by the non-volatile memory; and write the received data to the selected first segment.