Flash Data Path Architecture for Multi-Pass Programming Bandwidth
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Solution Overview
Problem
TLC NAND flash devices require multi-pass programming, which can be complex and inefficient due to the need for specific programming orders and the sharing of bandwidth in on-chip volatile memory, leading to system bandwidth limitations.
Innovation Solution
The use of an external off-chip volatile memory, such as DRAM, as an intermediate buffer to store encoded data for subsequent passes, allowing the on-chip SRAM to be released for faster data transfer with the host system, and implementing a write back channel and bypass channel to manage data traffic between the two volatile memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If on-chip volatile memory is used to store intermediate data for multi-pass programming, then data accessibility is improved, but system bandwidth is limited due to memory sharing
Solution Approach 1:
The patent introduces an external volatile memory as an intermediary component between the on-chip volatile memory and the flash device. This external memory acts as a buffer that stores intermediate data for multi-pass programming, allowing the on-chip memory to be released for host data transfers while the external memory handles the intermediate data storage and retrieval operations.
2Adaptability or versatility
If a dedicated buffer is allocated for TLC NAND flash device, then multi-pass programming is enabled, but system bandwidth suffers due to data retrieval from buffer
Solution Approach 1:
The patent extends the memory hierarchy by adding an external volatile memory dimension outside the chip. This allows the system to maintain dedicated buffering capability for multi-pass programming while bypassing the bandwidth limitations of on-chip memory by utilizing the external memory's larger capacity and different access characteristics.
3Reliability
If on-chip memory is used for both host data transfer and intermediate data storage, then data availability is ensured, but bandwidth utilization is reduced
Solution Approach 1:
The patent segments the memory functions by separating host data transfer operations from intermediate data storage operations. The on-chip volatile memory is dedicated to host data transfers, while the external volatile memory handles intermediate data storage for multi-pass programming. This segmentation eliminates resource contention and allows both functions to operate at full bandwidth utilization.
Data Source
AI summary
Efficient data path architecture for flash devices requiring multi-pass programming utilizes an external memory as an intermediate buffer to store the encoded data used for a first pass programming of the flash device. The stored encoded data can be read from the external memory for subsequent passes programming instead of fetching the data from an on-chip memory, which stores the data received from a host system. Thus, the on-chip memory can be made available to speed up the next data transfer from the host system.