Flash Memory Debug Circuit for External Error Simulation
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Solution Overview
Problem
Conventional flash memory controllers generate and check debug information internally, leading to unreliable test results without external involvement from the flash memory device, which can result in inaccurate error handling.
Innovation Solution
A flash memory device with an I/O control circuit, command and address registers, memory cell array, status register, and control circuit that generates and transmits debug information to the controller via a communication interface, allowing for simulated or true error simulation without affecting the memory cell array, enhancing error handling accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the flash memory controller generates and checks debug information internally, then the controller can perform error handling, but the test results are unreliable due to lack of external involvement from the flash memory device
Solution Approach 1:
The debug functionality is segmented between the flash memory controller and the flash memory device. The flash memory device includes a dedicated debug circuit that independently generates debug information, separating the debug generation function from the controller's firmware component. This segmentation allows external verification and improves test result reliability.
Solution Approach 2:
A debug circuit is introduced as an intermediary component within the flash memory device. This intermediary automatically generates debug information based on access commands and transmits it to the controller, serving as a mediator that provides objective external verification without requiring complex manual testing procedures.
2Measurement precision
If the debug circuit controls the voltage generator to make the memory cell array generate errors, then true error conditions can be simulated, but actual memory cell array errors occur which may affect normal operation
Solution Approach 1:
The debug circuit creates a copy or simulation of error conditions rather than directly causing actual errors in the memory cell array. By generating debug information that represents potential failures without physically corrupting memory cells, the system can test error handling while preserving normal memory operation.
Solution Approach 2:
The error generation function is extracted from the voltage generator and memory cell array system. Instead of using the voltage generator to create actual physical errors in the memory cells, the debug circuit extracts the error simulation function and implements it through logical debug information generation, separating the testing function from the actual memory storage function.
Data Source
AI summary
A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends an error injection set-feature signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of an access command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, with actually controlling a memory cell array of flash memory device generating failure errors.