Flash Memory Decoder Circuit With Variable-Domain Syndrome Rotation
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Solution Overview
Problem
Conventional decoder circuits in flash memory controllers require two traditional barrel shifters, leading to high circuit design complexity and delay stages that affect calculation accuracy and implementation.
Innovation Solution
A decoder device with a syndrome calculation check circuit, first and second barrel shifters, variable weighted-sum calculation circuit, and flipping circuit, which perform rotations within the variable node domain only, reducing circuit complexity and costs by allowing parallel operations and eliminating the need for rotations between variable and check node domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two traditional barrel shifter circuits are used for rotation calculation between variable node domain and check node domain, then the decoding function is achieved, but the circuit design complexity increases and delay stages multiply
Solution Approach 1:
The patent extracts and eliminates the check node domain from the rotation calculation process. Instead of rotating between variable node domain and check node domain as in traditional methods, the invention performs rotation operations solely within the variable node domain, thereby removing the complexity associated with dual-domain transformations while maintaining decoding functionality
Solution Approach 2:
The patent segments the decoding process into independent variable node processing units. Each variable node Vi has its own syndrome calculation check circuit and barrel shifter that operate independently, allowing parallel processing without requiring coordinated rotation between different node domains, thus reducing overall circuit complexity
2Reliability
If two traditional barrel shifter circuits are located in the same circuit loop, then the rotation operations are performed, but many delay stages are inevitable and calculation accuracy is greatly affected
Solution Approach 1:
The patent introduces dynamic parallel processing where multiple variable node processing units operate simultaneously rather than sequentially in a single circuit loop. This dynamic approach eliminates the accumulation of delay stages by allowing syndrome calculations and rotations for multiple nodes to proceed concurrently, thereby maintaining calculation accuracy
Solution Approach 2:
The patent transitions from a single-circuit-loop sequential architecture to a multi-dimensional parallel architecture where multiple processing units operate in parallel dimensions. This dimensional change allows simultaneous syndrome calculations and barrel shifter operations across different variable nodes, eliminating the delay stage bottleneck of the traditional single-loop design
3Reliability
If mutual rotation operation between variable node domain and check node domain is performed, then the decoding calculation is completed, but the circuit design complexity becomes high and implementation is difficult
Solution Approach 1:
The patent extracts and removes the check node domain from the rotation calculation process. Instead of rotating between variable node domain and check node domain as in traditional methods, the invention performs rotation operations solely within the variable node domain, thereby removing the complexity associated with dual-domain transformations while maintaining decoding functionality
Solution Approach 2:
The patent applies homogeneity by performing all rotation operations within the same variable node domain rather than switching between different domains. This uniform approach simplifies the circuit design as all processing units operate under the same domain constraints, making the system easier to manufacture and implement compared to heterogeneous dual-domain approaches
Data Source
AI summary
A decoding method includes: using a syndrome calculation check circuit to calculate a syndrome value of variable node Vi of a parity check matrix based on multiple input bits; rotating the syndrome value of variable node Vi into the direction of variable node Vi+1 to generate an estimated syndrome value of variable node Vi+1; rotating the syndrome value of variable node Vi−1 into the direction of variable node Vi−Δ to generate a rotated syndrome information; performing a weighted-sum calculation based on multiple rotated syndrome information to generate a flipping function value; and comparing the flipping function value with a flipping threshold to generate a flipping result; the syndrome calculation check circuit determines whether to modify/flip a specific bit according to the flipping result.