Flash Memory Decoding for High-Reliability Error Addresses
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Solution Overview
Problem
The 3D NAND-type flash memory modules experience high reliability errors (HRE) due to short-circuit issues between bit lines and word lines, leading to decoding failures and increased decoding burdens, especially as P/E cycles increase.
Innovation Solution
A decoding method that reads and decodes data from flash memory modules, identifies specific addresses with high reliability errors, and modifies data accordingly to correct initial bit values, using a flash memory controller with a decoder that records physical addresses of errors and employs LDPC decoding to mitigate decoding failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D NAND-type flash memory module is used to improve storage density, then storage capacity is improved, but high reliability errors occur due to short-circuit issues between bit lines and word lines
Solution Approach 1:
The patent performs preliminary identification of high reliability error addresses by comparing decoding results with reliability information before final data retrieval. This preliminary action allows the system to proactively detect and flag addresses prone to short-circuit errors, enabling corrective measures to be taken in advance rather than reacting to errors after they occur.
Solution Approach 2:
The patent implements a feedback mechanism where reliability information from initial decoding attempts is fed back into the system to identify patterns of high reliability errors. This feedback loop allows the controller to learn from previous decoding outcomes and adjust its error handling strategy for subsequent operations on the same or similar addresses, improving overall system reliability.
2Productivity
If soft decoding is performed on data with high reliability errors, then decoding process is initiated, but decoding failure occurs due to incorrect initial bit values
Solution Approach 1:
The patent performs preliminary identification of high reliability error addresses by comparing decoding results with reliability information before final data retrieval. This preliminary action allows the system to proactively detect and flag addresses prone to short-circuit errors, enabling corrective measures to be taken in advance rather than reacting to errors after they occur.
Solution Approach 2:
The patent applies preliminary anti-action by identifying addresses with high reliability errors and applying corrective measures before the errors can cause decoding failure. The system proactively counteracts the potential harm of incorrect initial bit values by detecting suspicious addresses early and handling them with specialized error correction procedures.
3Device complexity
If conventional decoding method is used, then decoding operation is simple, but decoding burden increases due to high reliability errors
Solution Approach 1:
The patent segments the decoding process into distinct phases: initial decoding to obtain reliability information, identification phase to detect high reliability error addresses, and corrective decoding phase for flagged addresses. This segmentation allows the system to apply different levels of processing intensity to different data portions, reducing overall decoding burden by focusing complex error correction only where needed.
Solution Approach 2:
The patent applies local quality by treating different addresses differently based on their error characteristics. Instead of applying uniform complex error correction to all data, the system identifies specific addresses with high reliability errors and applies enhanced processing only to those locations, while leaving other addresses to undergo simpler decoding procedures.
Data Source
AI summary
The present invention provides a decoding method of a flash memory controller, wherein the decoding method includes the steps of: reading first data from a flash memory module; decoding the first data, and recording at least one specific address of the flash memory module according to decoding results of the first data, wherein said at least one specific address corresponds to a bit having high reliability errors (HRE) of the first data; reading second data from the flash memory module; and decoding the second data according to said at least one specific address.