Flash Memory Decoding Using Syndrome Weight and Partial RAID

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Solution Overview

Problem

The increasing probability of flash memory modules failing to be successfully decoded by low-density parity-check (LDPC) codes due to the shrinking process of flash memory, leading to increased usage of RAID decoding and prolonged decoding times, which decreases decoding efficiency.

Innovation Solution

A flash memory controller employs an efficient RAID decoding method that reads data from multiple chunks across different data planes, performs decoding operations, and determines whether to continue or give up decoding based on syndrome weights, utilizing syndrome weights to decide on the necessity of further decoding attempts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If flash memory process shrinks and develops towards 3-dimensional array, then storage capacity increases, but the probability of decoding failure by LDPC code increases significantly

Engineering Contradiction:
Improvestorage capacityVSAvoiddecoding success probability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the data storage structure into multiple data planes, blocks, data pages, and chunks. This hierarchical segmentation allows the system to apply different decoding strategies at different levels, using LDPC for chunks and RAID for data pages, thereby maintaining reliability in 3D flash memory with higher storage capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs a composite decoding approach that combines LDPC decoding and RAID decoding methods. By using both decoding techniques together rather than relying on a single method, the system achieves both high storage capacity utilization and improved decoding reliability in 3D flash memory structures.

Inventive Principle:
Principle #40Composite materials

2Reliability

If RAID decoding is used more frequently to compensate for LDPC failures, then decoding reliability improves, but decoding time increases significantly

Engineering Contradiction:
Improvedecoding success probabilityVSAvoiddecoding time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial RAID decoding by first attempting LDPC decoding on individual chunks, and only invoking RAID decoding at the data page level when LDPC fails. This partial application of RAID decoding reduces the overall decoding time while maintaining reliability by avoiding unnecessary RAID operations on successfully decoded data.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent implements a feedback mechanism where the decoding result of each chunk is evaluated, and based on this feedback, the system decides whether to proceed with RAID decoding at the data page level. This feedback-driven approach optimizes decoding time by avoiding redundant decoding operations while ensuring reliability when needed.

Inventive Principle:
Principle #23Feedback

3Reliability

If traditional RAID decoding method is used without syndrome weight optimization, then decoding completeness is maintained, but decoding efficiency decreases

Engineering Contradiction:
Improvedecoding completenessVSAvoiddecoding efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the parameter evaluation criterion by introducing syndrome weight as a key metric. By calculating and comparing syndrome weights of different chunks, the system identifies the most promising chunks for RAID decoding, thereby improving decoding efficiency while maintaining completeness through optimized parameter selection and evaluation.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12585585B2Memory device control method and associated apparatus for efficient decoding in using syndrome weight
Publication Date: 2026.03.24 SILICON MOTION INC
  • US12585585B2 patent drawing
  • US12585585B2 patent drawing
  • US12585585B2 patent drawing

AI summary

A control method of a memory device includes: reading and decoding first data of a first chunk, wherein the first chunk is located in a first data page of a super data page, and the super data page includes multiple data pages respectively located in multiple data planes; in response to the first chunk failing to be decoded, obtaining data of multiple corresponding chunks of the first chunk, wherein the multiple corresponding chunks are located in other data pages of the super data page; and in response to all of the data in the multiple corresponding chunks not being successfully decoded, determining whether to give up the decoding operation of the first chunk according to a symptom weight of the first chunk and at least one symptom weight of at least one corresponding chunk.