Flash Device Programming Interrupts to Reduce High-Priority Read Latency

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Solution Overview

Problem

Existing storage systems face inefficiencies in managing flash-based storage operations, leading to increased latency due to unnecessary write operations and lack of direct control by the operating system, which results in redundant processes and reduced reliability.

Innovation Solution

Implementing a direct-mapped flash storage system where the operating system directly addresses data blocks without translation by lower-level controllers, managing operations such as data rewriting and erasure, and utilizing non-volatile RAM for fast-write buffering to reduce latency and improve reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a traditional flash storage system with lower-level controllers is used, then data translation and buffering operations can be performed, but latency increases due to redundant write operations and lack of direct OS control

Engineering Contradiction:
Improvestorage operation reliabilityVSAvoidstorage operation latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the translation and buffering functions from the lower-level flash storage controller and relocates them to the operating system. This allows the OS to directly manage flash storage operations, eliminating redundant translation layers and reducing latency while maintaining data integrity through direct control

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a direct communication interface between the operating system and flash storage device, bypassing traditional lower-level controllers. This intermediary mechanism enables the OS to issue commands directly to the flash storage, reducing the number of intermediate processing steps and minimizing operation latency

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the operating system directly manages flash storage operations, then latency is reduced and control is improved, but system complexity increases

Engineering Contradiction:
Improvestorage operation speedVSAvoidstorage system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a universal interface layer in the operating system that can directly communicate with multiple flash storage devices using standardized commands. This multi-functional approach allows the same OS module to manage various flash storage operations (read, write, erase, validate) across different devices, reducing complexity through standardization rather than requiring device-specific control logic

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If redundant write operations are performed by lower-level controllers, then data buffering can be achieved, but flash device lifespan is reduced due to excessive program cycles

Engineering Contradiction:
Improvedata integrityVSAvoidflash device lifespan
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent implements validation logic in the operating system that checks whether data needs to be rewritten before issuing program commands to the flash storage. By performing this preliminary validation, the system avoids redundant write operations that would unnecessarily consume program cycles and reduce flash device lifespan, while still ensuring data integrity through selective rewriting

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12393340B2Latency reduction of flash-based devices using programming interrupts
Publication Date: 2025.08.19 PURE STORAGE INC
  • US12393340B2 patent drawing
  • US12393340B2 patent drawing
  • US12393340B2 patent drawing

AI summary

A read request with a high priority indication is received. A determination as to whether an in progress flash programming operation would delay processing the read request for a threshold amount of time is made. In response to determining that the in progress flash programming operation delays processing the read request for the threshold amount of time, the in progress flash programming operation is interrupted.