Flash Memory Disturb-Strength Matrix for Charge Error Management
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Solution Overview
Problem
Flash memory devices suffer from degradation mechanisms that lead to errors due to charge disturbances during program/erase cycles, with Multi-Level Cell (MLC) devices having lower endurance than Single-Level Cell (SLC) devices and experiencing 'read disturb' errors, which existing error detection and correction techniques struggle to address efficiently without impacting readout performance.
Innovation Solution
A Flash memory device and method using a disturb-strength matrix to assess the sensitivity of operations to charge disturbances, determining the relative strength of operations that cause errors, and incorporating a historical record of charge-disturbing operations to predict and correct errors in real-time, thereby extending the operational life and reliability of Flash memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing error detection and correction techniques are used, then data reliability is improved, but readout performance is impacted
Solution Approach 1:
The patent applies preliminary action by performing refresh operations before actual read operations occur. The controller proactively identifies blocks that need refreshing based on disturb count thresholds and schedules refresh operations in advance, ensuring data integrity is maintained without interfering with subsequent readout operations. This prevents errors from developing rather than correcting them after they occur.
Solution Approach 2:
The patent segments the flash memory array into multiple blocks, each with its own disturb count tracker. By organizing data management at the block level rather than at the chip level, the system can independently manage and refresh specific blocks that require attention, leaving other blocks available for normal readout operations. This segmentation enables parallel processing of reliability maintenance and data access functions.
2Quantity of substance
If MLC Flash devices are used, then storage density is improved, but program/erase cycles endurance deteriorates
Solution Approach 1:
The patent implements feedback mechanisms through continuous monitoring of disturb counts for each block. The controller reads disturb count values from metadata structures after each program/erase cycle and compares them against predetermined thresholds. When thresholds are approached, the system triggers refresh operations or adjusts future operations to prevent further disturbance accumulation, creating a closed-loop feedback system that adapts to the degrading state of MLC cells.
Solution Approach 2:
The system performs preliminary refresh operations before cumulative disturbances cause actual data errors. By monitoring disturb counts and initiating corrective actions in advance, the system prevents the degradation that would otherwise limit the operational life of MLC devices, effectively extending their usable program/erase cycle count.
3Ease of operation
If read operations are performed frequently, then data accessibility is improved, but charge disturbances accumulate
Solution Approach 1:
The patent uses feedback from disturb count monitoring to detect when read operations have accumulated sufficient disturbances to potentially cause errors. The controller continuously tracks the number of read operations on each block and compares it against threshold values that indicate dangerous disturbance levels, enabling proactive intervention before errors occur.
Solution Approach 2:
The system performs preliminary refresh operations when disturb counts approach dangerous thresholds, even before actual read errors occur. This preliminary corrective action resets the disturbance accumulation counter and prevents further harmful effects, allowing the system to tolerate frequent read operations while maintaining data integrity.
Data Source
AI summary
A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix should also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which changes in the measured dispersion value are provoked by executing a selected operation until a detectable change occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population.