Flash-DRAM Hybrid Memory Module With Integrated Data Buffering
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Solution Overview
Problem
Existing memory systems face data transfer bottlenecks due to the disparity in access speeds between Flash and DRAM, leading to inefficient CPU utilization and reduced server performance, with existing solutions like EcoRAM™ occupying CPU sockets and limiting throughput rates.
Innovation Solution
A hybrid memory module combining Flash and DRAM with an integrated controller and data manager to manage data transfer between volatile and non-volatile memory subsystems, optimizing data flow and addressing the speed disparity through buffering and buffering data transfer between the two types of memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If Flash memory is used for non-volatile storage, then data retention capability is improved, but access speed deteriorates
Solution Approach 1:
The patent combines Flash memory and DRAM into a hybrid memory module that presents a unified interface to the CPU. The controller manages data between the two memory types, allowing the system to leverage both the non-volatile storage capability of Flash and the high-speed access of DRAM through a single integrated architecture.
Solution Approach 2:
The controller acts as an intermediary between the CPU and the hybrid memory subsystem. It translates CPU requests into appropriate operations for either Flash or DRAM, manages data buffering between the two memory types, and handles address mapping, thereby hiding the speed disparity from the CPU and optimizing overall access performance.
2Productivity
If existing solutions like EcoRAM™ are used to bridge Flash and DRAM, then data transfer capability is improved, but CPU socket availability deteriorates
Solution Approach 1:
The hybrid memory module is designed to occupy a standard memory slot while providing multiple functions: it acts as both volatile and non-volatile memory, presents a unified interface to the CPU, and includes integrated data management capabilities. This eliminates the need for separate CPU sockets or additional controller hardware.
3Reliability
If Flash access speed directly limits memory operations, then data transfer bottleneck is improved, but overall system performance deteriorates
Solution Approach 1:
The controller performs preliminary actions by pre-fetching data from Flash to DRAM buffer before the CPU needs it, and by maintaining ready-state data in the DRAM portion of the hybrid module. This reduces wait states and ensures that high-speed data transfer can occur without being bottlenecked by Flash access speeds during active CPU operations.
Data Source
AI summary
In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.