Flash Memory ECC Controller with Selective BCH-RS Decoding
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Solution Overview
Problem
Flash memory devices face significant errors in reading multi-bit data due to overlapping threshold voltage distributions, which increase with the number of bits stored, leading to unreliable data retrieval.
Innovation Solution
The implementation of ECC controllers that generate and store first and second error correction codes, allowing selective correction of errors based on the number of errors detected, using a high-speed BCH code for fewer errors and a high-performance RS code for more errors, to enhance data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit data is stored in each memory cell to increase storage capacity, then the storage density is improved, but the error rate increases due to overlapping threshold voltage distributions
Solution Approach 1:
The error correction process is segmented into two distinct stages: first ECC correction for 1-bit errors and second ECC correction for multi-bit errors. This segmentation allows the system to handle different error types with appropriate correction methods, improving overall reliability while maintaining multi-bit storage capacity
Solution Approach 2:
First ECC data is generated and stored alongside the multi-bit data before reading operations. This preliminary error correction code is specifically designed to correct 1-bit errors, which are the most common error type in flash memory, thereby preventing these errors from propagating and reducing the burden on subsequent correction stages
2Reliability
If a single strong error correction code is used to correct all errors, then the error correction capability is improved, but the decoding complexity and time increase
Solution Approach 1:
The error correction code system is divided into two separate ECC schemes: first ECC with simpler decoding for common 1-bit errors, and second ECC with more complex decoding for rare multi-bit errors. This segmentation reduces the average decoding complexity while maintaining comprehensive error correction capability
Solution Approach 2:
The first ECC is designed to handle the majority of error cases (1-bit errors) with a simplified correction approach. Only when the first ECC determines that errors exceed its correction capability does the system activate the second ECC, avoiding the overhead of always using the more complex correction method
3Device complexity
If a single error correction code is used for all error cases, then the system design is simplified, but the correction speed varies for different error amounts
Solution Approach 1:
The error correction system dynamically selects between first ECC and second ECC based on the detected error pattern and magnitude. The decoding controller adapts the correction strategy in real-time, using the faster first ECC for simple cases and the more powerful second ECC only when necessary, thereby optimizing overall correction speed
Solution Approach 2:
The system replaces a static, single-error-correction-code approach with a dynamic, conditional correction system that substitutes mechanical always-on complex decoding with intelligent error pattern recognition and selective correction method activation
Data Source
AI summary
An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.