Flash Memory ECC Controller Using Row-Column Parity Checks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing Flash memory technologies, particularly Multiple Level Cell (MLC) Flash memories, face challenges in utilizing storage space efficiently due to the increased costs and chip area associated with enhancing error correction capabilities, as increasing the Error Correction Code (ECC) engine encoding/decoding bit count leads to wastefulness in storage space utilization.
Innovation Solution
A method that calculates first and second parity codes across rows and non-overlapping sets of columns in a data bit array, utilizing a microprocessor and control logic to enhance error correction capability without increasing the ECC engine encoding/decoding bit count, allowing for efficient use of remaining storage space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ECC engine encoding/decoding bit count is increased to enhance error correction capability, then the error correction capability is improved, but the chip area and costs are greatly increased
Solution Approach 1:
The data bit array is divided into multiple rows and columns, with parity codes calculated separately for each row and column set. This segmentation allows the ECC engine to process smaller, manageable units of data independently, reducing the required encoding/decoding bit count while maintaining comprehensive error correction coverage across the entire data array.
Solution Approach 2:
The patent introduces a two-dimensional parity check structure by calculating parity codes across both rows and columns of the data bit array. This dimensional approach enables error detection and correction through multiple perspectives, achieving enhanced error correction capability without proportionally increasing the ECC engine's bit count, as the same parity bits serve multiple checking purposes.
2Reliability
If the ECC engine encoding/decoding bit count is increased to enhance error correction capability, then the error correction capability is improved, but the storage space utilization is reduced
Solution Approach 1:
By segmenting the data into rows and columns with overlapping parity checks, the patent reduces the total number of parity bits required compared to traditional single-dimension ECC schemes. This segmentation allows more of the Flash memory capacity to be used for actual data storage while maintaining robust error correction through the multi-dimensional parity structure.
Solution Approach 2:
The parity codes calculated for row and column checks serve multiple functions simultaneously - they detect errors in their respective dimensions and enable error correction through the intersection of failed checks. This multi-functionality reduces the overhead of error correction code bits, thereby improving storage space utilization while maintaining high error correction capability.
3Quantity of substance
If traditional error correction methods are used to utilize all storage space, then storage space utilization is improved, but the error correction capability is insufficient
Solution Approach 1:
The patent implements a two-dimensional error correction structure where parity codes are calculated across both rows and columns of the data array. This dimensional approach enables the system to detect and correct errors using the intersection of row and column parity checks, achieving superior error correction capability without significantly increasing storage overhead, thus maintaining high storage space utilization.
Solution Approach 2:
By dividing the data array into manageable rows and columns with distributed parity checks, the patent achieves comprehensive error correction coverage across the entire storage space. This segmentation allows errors to be detected and corrected locally through row-column intersection, providing robust error correction capability while utilizing nearly all available storage space for data.
Data Source
AI summary
A method for enhancing error correction capability of a controller of a memory device without increasing an Error Correction Code (ECC) engine encoding/decoding bit count includes: regarding a plurality of rows of a data bit array, respectively calculating a plurality of first parity codes; regarding a plurality of sets of columns of the data bit array, respectively calculating a plurality of second parity codes, wherein each set of the sets includes two or more of the columns, and the sets do not overlap; and performing encoding/decoding corresponding to the first and the second parity codes. An associated memory device and the controller thereof are further provided.