Flash Memory ECC Decoder Using Syndrome Division for Faster Reads
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Solution Overview
Problem
High-speed error correction in non-volatile semiconductor memory devices is hindered by latency issues due to the time-consuming processes of detecting and correcting errors in multi-bit data storage, particularly in flash memory systems.
Innovation Solution
A memory system and method incorporating an error correction decoder with a syndrome computation circuit, an error correction and computation circuit, and an error correction circuit that calculates and corrects single-bit errors through division operations between syndrome elements, thereby reducing latency and increasing error correction speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction methods are used in multi-bit flash memory devices, then error correction capability is provided, but latency increases and correction speed decreases
Solution Approach 1:
The patent segments the error correction process into distinct stages: syndrome computation, error location determination, and error correction. By dividing the correction process and handling single-bit and multi-bit errors through different pathways, the system reduces overall latency while maintaining comprehensive error correction capability.
Solution Approach 2:
The patent performs preliminary syndrome computation during the read operation itself, rather than waiting until after the full read completes. This preliminary action allows error detection and correction to begin in parallel with data retrieval, significantly reducing the effective latency of the error correction process.
2Reliability
If high performance ECC circuits are used to correct errors in read data, then error correction capability is improved, but integration complexity increases
Solution Approach 1:
The ECC circuit is segmented into specialized sub-circuits for different error types: a syndrome computation circuit for generating syndromes, an error location circuit for determining error positions using division operations, and separate correction pathways for single-bit and multi-bit errors. This segmentation allows each sub-circuit to be optimized independently, improving overall performance while managing integration complexity.
Solution Approach 2:
The patent implements a selective error correction approach where single-bit errors are handled through a simplified, faster pathway using division operations on syndrome elements, while multi-bit errors receive more comprehensive correction. This partial action strategy provides high-performance correction for the most common error type without fully implementing complex correction mechanisms for all possible error scenarios, thereby reducing integration complexity.
3Quantity of substance
If multi-bit data storage is implemented in flash memory cells, then integration density increases, but error probability increases
Solution Approach 1:
The patent implements a feedback mechanism where syndromes are continuously computed from read data, error locations are determined based on these syndromes, and corrections are applied and verified. This closed-loop feedback system enables the memory system to detect and correct errors that arise from multi-bit storage, maintaining reliability despite the increased error probability inherent in higher-density cells.
Solution Approach 2:
The patent employs inexpensive and simple error correction techniques such as syndrome computation using division operations and lookup tables for error location determination. These lightweight correction mechanisms provide adequate protection against errors in multi-bit cells without requiring complex, resource-intensive correction codes, thus maintaining system efficiency while handling the increased error rate from high-density storage.
Data Source
AI summary
An error correction decoder includes a syndrome computation circuit, an error correction and computation circuit and an error correction circuit. The syndrome computation circuit calculates a syndrome of read data. The error correction and computation circuit calculates a location of a single-bit error using a division operation between elements of the syndrome when the single-bit error exists in the read data. The error correction circuit corrects the single-bit error of the read data based on the location of the single-bit error.