Flash EEPROM Threshold Voltage Trimming via Band-to-Band Tunneling
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Solution Overview
Problem
Conventional methods for programming and trimming threshold voltages in Multi-Level-Cell (MLC) flash memory cells face challenges in precise charge placement, sensing, and stable storage, leading to misreading due to over-programming and inability to adjust threshold voltages with small enough increments to maintain desired voltage bands.
Innovation Solution
The method involves applying specific voltage biases and pulses to the control gate, drain, and body terminals of NVM cells to trim down the threshold voltages of over-programmed cells, ensuring they fall within the desired voltage band by adjusting pulse durations and amplitudes, allowing for precise control of charge placement and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional programming methods are used to program MLC cells, then the threshold voltage can be adjusted, but the threshold voltage distribution becomes wide causing misreading between neighboring levels
Solution Approach 1:
The programming process is divided into multiple stages with intermediate verification. After each programming pulse, the threshold voltage is measured and cells are sorted into groups based on their threshold voltage levels. This segmentation allows precise control of charge placement by addressing each group separately and preventing over-programming that would cause threshold voltage distribution to exceed neighboring level boundaries.
Solution Approach 2:
A verification reading process is implemented after programming to measure the actual threshold voltage of each cell. The measured threshold voltage is compared with the target level, and feedback is used to adjust subsequent programming operations. This feedback mechanism ensures that threshold voltage distribution remains within acceptable margins for reliable differentiation between neighboring levels.
2Quantity of substance
If the threshold voltage range is increased to accommodate more bits per cell, then the storage density improves, but the separation between threshold levels must be larger reducing the number of usable levels
Solution Approach 1:
The system dynamically adjusts the programming parameters including pulse amplitude, pulse width, and inter-pulse delays based on the specific target threshold voltage level and the current state of the cell array. This dynamic programming approach allows efficient utilization of the full threshold voltage range to accommodate more bits per cell while maintaining adequate separation between levels through adaptive control rather than fixed margins.
3Productivity
If programming voltage biases are increased to ensure sufficient charge injection, then the programming speed improves, but the threshold voltage distribution widens due to non-uniform cell responses
Solution Approach 1:
Different programming pulse parameters are applied to different groups of cells based on their measured threshold voltage characteristics. Cells with lower threshold voltages receive different pulse amplitudes and durations compared to cells with higher threshold voltages. This local quality approach ensures that each cell receives the precise amount of charge needed to reach its target level, maintaining uniformity across the array while preserving high programming speed through parallel processing of multiple groups.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of charge placement and storage, increasing digital storage density by ensuring threshold voltages are accurately trimmed within the desired range, preventing misreading and enhancing data retention in MLC operations.
Implementation Method 1
the reversed bias of the body-drain junction generates band to band tunneling to cause the stored charges to be annihilated in or released from the storing material
Data Source
AI summary
A method of trimming FET NVM cells in Multi-Level-Cell (MLC) operation is provided. The method comprises (a) applying a first voltage and a second voltage to a control gate and a bulk of the over-programmed FET NVM cell, respectively; and (b) applying a signal to a drain of the over-programmed FET NVM cell for a time period to produce a limited threshold voltage reduction; wherein polarities of the first voltage and the second voltage are opposite to that of the signal. Thus, the charge placement in the storing material could be precisely controlled within a small range of charge state and produce a multi-bits/cell of higher digital storage density.