Flash EEPROM Erase Method Using Two-Stage Voltage Biasing
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Solution Overview
Problem
Existing flash memory cell erase techniques rely on high electrical fields, leading to reliability issues such as 'hot hole' injection, Time Dependent Dielectric Breakdown, and performance degradation due to the need for strong electric fields across the dielectric, which limits device scaling and operation voltage levels.
Innovation Solution
A two-stage erase method is introduced, where a positive voltage is applied to the well terminal to deplete charge from mobile traps, followed by a negative voltage applied to the control gate to remove charge from the floating gate through tunneling, utilizing weaker electric fields and shorter pulse durations, thereby reducing the vulnerability to electrical stress-induced reliability issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high electrical fields are applied across the dielectric to achieve tunneling erase, then erase efficiency is improved, but reliability deteriorates due to hot hole injection and Time Dependent Dielectric Breakdown
Solution Approach 1:
The erase operation is divided into two sequential stages: first applying positive voltage to the well terminal to deplete mobile traps, then applying negative voltage to the control gate for charge removal. This segmentation allows each stage to operate with lower electric field strength, reducing hot hole injection while maintaining effective erase functionality.
Solution Approach 2:
The positive voltage pulse applied to the well terminal serves as a preliminary action that depletes mobile traps before the main erase operation. This preparatory step reduces the population of mobile charges that would otherwise be accelerated by high electric fields during tunneling, thereby minimizing hot hole injection and dielectric damage.
2Speed
If strong electric fields are used to generate sufficient tunneling current, then erase speed is improved, but device degradation increases due to interface state generation and dielectric trap formation
Solution Approach 1:
The invention changes the voltage application parameters by first applying positive voltage to the well terminal, which modifies the electric field distribution and depletes mobile traps. This parameter change enables subsequent tunneling to occur with lower peak electric fields, maintaining erase speed while reducing interface state generation and dielectric trap formation.
3Productivity
If high voltage pulses are applied simultaneously to control gate and source region, then charge removal is accelerated, but hot hole tunneling current increases causing dielectric breakdown
Solution Approach 1:
The simultaneous voltage application is segmented into sequential stages: first positive voltage to the well terminal, then negative voltage to the control gate. This eliminates the condition for hot hole tunneling while maintaining effective charge removal through the depleted trap state.
Solution Approach 2:
The positive voltage pulse to the well terminal acts as a preliminary anti-action that depletes mobile traps and reduces the conditions favorable for hot hole tunneling before the negative gate voltage is applied, thereby preventing dielectric breakdown while maintaining charge removal efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for higher tunneling currents without the need for strong electric fields, increasing immunity to reliability issues by using electric fields that are about half the magnitude and duration of those in prior art methods, thus improving erase efficiency and reducing device degradation.
Implementation Method 1
Erasing the cell is done by removing the charge usually by means of tunneling. This technique is usually referred to as Negative Gate Source Erase (NGSE). The electrical field formed across the dielectric layer 19 between the floating gate and the substrate would yield a tunneling current draining the electrons stored in the floating gate.
Implementation Method 2
Implementation of tunneling erase techniques requires the usage of large electrical field across the dielectric between the floating gate and the well.
Implementation Method 3
Since the source region 16 is reversed biased during the erase operation, a band to band tunneling current is present at the surface 17. This tunneling current produces energetic holes that are attracted by the floating gate to source electric field and have a probability for tunneling into the floating gate.
Data Source
AI summary
The invention is a new method for erasing a flash EEPROM memory device. The memory device has a first semiconductor region within a second semiconductor region, source and drain regions in the first semiconductor region, a well terminal inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer, and a control terminal electrically isolated from the charge storing layer by a inter layer dielectric. The method comprises the steps of: applying a first voltage bias of first polarity to the well terminal; allowing a first time period to elapse; applying a second voltage bias of second polarity opposite to the first polarity to the control terminal; resetting the first voltage bias to zero; allowing a second time period to elapse; and resetting the second voltage bias to zero.