Flash Memory Emulation Using SoC Storage for Faster FPGA Testing
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Solution Overview
Problem
The existing technologies for programming and testing FPGAs are hindered by slow write times and limited endurance of flash memory devices, making it costly and inefficient for high-volume testing and requiring numerous devices.
Innovation Solution
A circuit arrangement and method that emulates a flash memory device using a system-on-chip (SoC) with multiple storage circuits, an input-output circuit, an emulator circuit, and a translator circuit, allowing for faster configuration and reduced costs by eliminating the need for physical flash memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flash memory devices are used to store configuration data for FPGA testing, then data storage is achieved, but write time becomes excessively slow (several minutes per configuration)
Solution Approach 1:
The patent creates a virtual copy of the flash memory device using multiple storage circuits (RAM, ROM, or other memory types) that emulate flash memory functionality. This virtual flash memory provides the same configuration data storage capability but with significantly faster write speeds, eliminating the bottleneck of physical flash memory programming during FPGA testing.
Solution Approach 2:
The patent introduces a flash emulator as an intermediary component between the FPGA and the physical storage system. This emulator translates flash memory commands into operations on faster storage circuits, mediating between the need for flash-like persistence and the desire for rapid configuration updates during testing.
2Quantity of substance
If physical flash memory devices are used for high-volume FPGA testing, then configuration storage is provided, but numerous devices and supporting hardware are required, increasing system complexity and cost
Solution Approach 1:
The patent merges multiple storage circuits (RAM, ROM, or other memory types) into a single virtual flash memory system that can serve multiple FPGAs simultaneously. This consolidation eliminates the need for numerous separate flash memory devices, reducing system complexity and cost while maintaining the ability to store configuration data for high-volume testing.
Solution Approach 2:
The virtual flash memory system provides universal functionality that can serve multiple FPGAs with different configuration requirements. A single emulated flash device can be dynamically reconfigured to test numerous different eFuse configurations across multiple FPGAs, replacing the need for dedicated flash devices for each testing scenario.
3Quantity of substance
If less expensive flash memory devices are used, then cost is reduced, but write endurance becomes limited (only a few hundred write cycles)
Solution Approach 1:
The patent creates a virtual copy of flash memory using storage circuits with superior endurance characteristics. By emulating flash memory functionality on media like RAM or ROM that can withstand millions of write cycles, the system achieves both low cost and high reliability without the limitations of physical flash memory device endurance.
4Ease of operation
If configuration data is written to flash memory for eFuse verification, then testing capability is provided, but the process becomes slow and costly
Solution Approach 1:
The patent creates a virtual flash memory environment that enables rapid eFuse configuration verification. By using faster storage circuits to emulate flash memory, the system can quickly write and verify configuration data for different eFuse settings, dramatically reducing testing time while maintaining full verification capability.
Data Source
AI summary
Disclosed approaches for emulating flash memory include storage circuits having respective address decoders. An input-output circuit has pins compatible with a flash memory device and is configured to input flash commands and output response signals via pins. An emulator circuit is configured to translate each flash command into one or more storage-circuit commands compatible with one storage circuit of the storage circuits, and to generate response signals compatible with the flash memory device. A translator circuit is configured to map a flash memory address in each flash command to an address of the one storage circuit, and to transmit the one or more storage-circuit commands and address to the one storage circuit.